dsPIC30F Family Reference Manual
DS70069C-page 22-24 © 2004 Microchip Technology Inc.
22.5.5.2 How to Determine the I
2
S Channel Alignment
Most I
2
S codecs support two channels of data and the level of the frame sync signal indicates
the channel that is transferred during that half of the data frame. The COFS pin can be polled in
software using its associated Port register to determine the present level on the pin in the DCI
Interrupt Service Routine. This will indicate which data is in the Receive register and which data
should be written to the Transmit registers for transfer on the next frame.
22.5.5.3 I
2
S Data Justification
As per the I
2
S specification, a data word transfer will by default begin one serial clock cycle
following a transition of the frame sync signal. An ‘MSb left-justified’ option can be selected using
the DJST control bit (DCICON1<5>).
If DJST = 1, the I
2
S data transfers will be MSb left justified. The MSb of the data word will be
presented on the CSDO pin during the same serial clock cycle as the rising or falling edge of the
FS signal. After the data word has been transmitted, the state of the CSDO pin is dictated by the
CSDOM (DCICON1<6>) bit.
The left-justified data option allows two stereo codecs to be connected to the same serial bus.
Many I
2
S compatible devices have configuration options for left-justified or right-justified data.
The word size selection bits are set to twice the codec word length and data is read/written to the
DCI memory in a packed format. The connection details for a dual I
2
S codec system are shown
in Figure 22-12.
Timing diagrams for I
2
S mode are shown in Figure 22-13. For reference, these diagrams assume
an 8-bit word size (WS<3:0> = 0111b). Two data words per frame would be required to achieve
a 16-bit sub-frame (COFSG<3:0> = 0001b). The 3rd timing diagram in Figure 22-13 uses packed
data to read/write from two codecs. For this example, the DCI module is configured for a 16-bit
data word (WS<3:0> = 1111b). Two packed 8-bit words are written to each 16-bit location in the
DCI memory buffer.
Figure 22-12: Dual I
2
S Codec Interface
dsPIC
®
Codec #1
SCK
FS
SDO
SCK
WS
SDI
Codec #2
SCK
WS
SDI
Device
I
2
C™/SPI™
I
2
C™/SPI™
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