© 2004 Microchip Technology Inc. DS70069C-page 22-25
Section 22. Data Converter Interface (DCI)
Data Converter
Interface (DCI)
22
Figure 22-13: I
2
S Data Justification Options
22.5.6 AC-Link Operation
This section describes how to use the DCI in the AC-Link modes. The AC-Link modes are used
to communicate with AC-’97 compliant codec devices.
22.5.6.1 AC-Link Data Frame
The AC-Link data frame is 256 bits subdivided into one 16-bit control slot, followed by twelve
20-bit data slots. The AC-’97 codec usually provides the serial transfer clock signal which is
derived from a crystal oscillator as shown in Figure 22-14. The controller receives the serial clock
and generates the frame sync signal. The default data frame rate is 48 kHz. The frame sync
signal used for AC-Link systems is high for 16 CSCK periods at the beginning of the data frame
and low for 240 CSCK periods. The data transfer begins one CSCK period after the rising edge
of the frame sync signal as shown in Figure 22-16. Data is sampled by the receiving device on
the falling edge of CSCK. The control and data time slots in the AC-Link have defined uses in the
protocol as shown in Figure 22-15. Refer to the Appendix of this manual or the Intel
®
AC ‘97
Codec Specification, Rev 2.2 for a complete definition of the AC-Link protocol.
765
43210
765
43210
Channel #1 Transfer
Channel #2 Transfer
CSCK
COFS
Data
765
43210
765
43210
Channel #1 Transfer
Channel #2 Transfer
CSCK
COFS
Data
765
43210
765
43210
Channel #1 Transfer, Word 1
CSCK
COFS
Data
765
43210 765
43210
1. Standard I
2
S Data Alignment
2. Left-Justified Data Alignment
3. Left-Justified Data Alignment with Packed Data
Channel #1 Transfer, Word 2
Channel #2 Transfer, Word 1 Channel #2 Transfer, Word 2
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