Microchip Technology dsPIC30F - Page 333

© 2004 Microchip Technology Inc. DS70062C-page 15-23
Section 15. Motor Control PWM
Motor Control
PWM
15
15.4.4 Center Aligned PWM
Center aligned PWM signals are produced by the module when the PWM time base is
configured in one of the two Up/Down Counting modes (PTMOD<1:0> = 1x).
The PWM compare output is driven to the active state when the value of the Duty Cycle register
matches the value of PTMR and the PWM time base is counting downwards (PTDIR = 1). The
PWM compare output will be driven to the inactive state when the PWM time base is counting
upwards (PTDIR = 0) and the value in the PTMR register matches the duty cycle value.
If the value in a particular Duty Cycle register is zero, then the output on the corresponding
PWM pin will be inactive for the entire PWM period. In addition, the output on the PWM pin will
be active for the entire PWM period if the value in the Duty Cycle register is greater than the
value held in the PTPER register.
Figure 15-8: Center Aligned PWM
15.4.5 Duty Cycle Register Buffering
The four PWM duty cycle registers, PDC1-PDC4, are buffered to allow glitchless updates of the
PWM outputs. For each generator, there is the PDCx register (buffer register) that is accessible
by the user and the non-memory mapped Duty Cycle register that holds the actual compare
value. The PWM duty cycle is updated with the value in the PDCx register at specific times in
the PWM period to avoid glitches in the PWM output signal.
When the PWM time base is operating in the Free Running or Single Event modes
(PTMOD<1:0> = 0x), the PWM duty cycle is updated whenever a match with the PTPER
register occurs and PTMR is reset to ‘0’.
When the PWM time base is operating in the Up/Down Counting mode (PTMOD<1:0> = 10),
duty cycles are updated when the value of the PTMR register is zero and the PWM time base
begins to count upwards. Figure 15-9 indicates the times when the duty cycle updates occur for
this mode of the PWM time base.
When the PWM time base is in the Up/Down Counting mode with double updates
(PTMOD<1:0> = 11), duty cycles are updated when the value of the PTMR register is zero and
when the value of the PTMR register matches the value in the PTPER register. Figure 15-10
indicates the times when the duty cycle updates occur for this mode of the PWM time base.
PTPER
PTMR
Value
Period
Period/2
0
PDC1
PDC2
PWM1H
PWM2H
PDCx
Value
Note: Any write to the PDCx registers will immediately update the duty cycle when the
PWM time base is disabled (PTEN = 0). This allows a duty cycle change to take
effect before PWM signal generation is enabled.