© 2004 Microchip Technology Inc. DS70062C-page 15-21
Section 15. Motor Control PWM
Motor Control
PWM
15
Figure 15-5: Duty Cycle Comparison Logic
15.4.2 Edge Aligned PWM
Edge aligned PWM signals are produced by the module when the PWM time base is operating
in the Free Running mode. The output signal for a given PWM channel has a period specified
by the value loaded in PTPER and a duty cycle specified by the appropriate PDCx register (see
Figure 15-6). Assuming a non-zero duty cycle, the outputs of all enabled PWM generators will
be driven active at the beginning of the PWM period (PTMR = 0). Each PWM output will be
driven inactive when the value of PTMR matches the duty cycle value of the PWM generator.
If the value in the PDCx register is zero, then the output on the corresponding PWM pin will be
inactive for the entire PWM period. In addition, the output on the PWM pin will be active for the
entire PWM period if the value in the PDCx register is greater than the value held in the PTPER
register.
Figure 15-6: Edge-Aligned PWM
PTMR N21 TCY
15-bit
comparison
PDCx
Edge
Logic
PWM Edge Event
14 0 N-bit Prescaler
15
15 1 0
15
1-Bit Comparison
Note: PDCx<0> is compared to the FOSC/2 signal when the prescaler is 1:1.
Period
Duty Cycle
0
PTPER
New duty cycle loaded from PDCx
PWM1H
PWM2H
PDC1
PDC2
PTMR value
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