Microchip Technology dsPIC30F - Page 548

dsPIC30F Family Reference Manual
DS70068C-page 21-34 © 2004 Microchip Technology Inc.
21.7.3.2 7-bit Address and Slave Read
When a slave read is specified by having R/W
= 1 in a 7-bit address byte, the process of
detecting the device address is similar to that for a slave write (see Figure 21-23). If the
addresses match, the following events occur:
1. An ACK
is generated.
2. The D_A bit is cleared and the R_W bit is set.
3. The module generates the SI2CIF interrupt on the falling edge of the ninth SCL clock.
Since the slave module is expected to reply with data at this point, it is necessary to suspend the
operation of the I
2
C bus to allow the software to prepare a response. This is done automatically
when the module clears the SCLREL bit. With SCLREL low, the slave module will pull down the
SCL clock line, causing a wait on the I
2
C bus. The slave module and the I
2
C bus will remain in
this state until the software writes the I2CTRN register with the response data and sets the
SCLREL bit.
Figure 21-23: Slave Read 7-bit Address Detection Timing Diagram
Note: SCLREL will automatically clear after detection of a slave read address regardless of
the state of the STREN bit.
SCL (Master)
SDA (Master)
SDA (Slave)
SI2CIF Interrupt
3 41 2
- Detecting Start bit enables
1
I
2
C Bus State
(S) (D) (D)
(A)(D) (Q)
A4A5A6 A3 A2 A1 A0
R/W
D_A
ADD10
SCLREL
R_W
address detection.
- R/W
= 1 bit indicates that slave
2
sends data bytes.
- Address match of first byte clears
3
D_A bit. Slave generates ACK
.
- R_W bit set. Slave generates
4
interrupt. SCLREL cleared.
5
- Bus waiting. Slave prepares to
5
send data.
=1
SCL (Slave)
Slave pulls SCL low while
SCLREL = 0.