Microchip Technology dsPIC30F - Page 549

© 2004 Microchip Technology Inc. DS70068C-page 21-35
Section 21. Inter-Integrated Circuit (I
2
C)
Inter-Integrated
Circuit (I
2
C)
21
21.7.3.3 10-bit Address
In 10-bit Address mode, the slave must receive two device address bytes (see Figure 21-24).
The five Most Significant bits (MSbs) of the first address byte specify a 10-bit address. The R/W
bit of the address must specify a write, causing the slave device to receive the second address
byte. For a 10-bit address the first byte would equal ‘11110 A9 A8 0’, where A9 and A8 are
the two MSbs of the address.
Following the Start condition, the module shifts 8 bits into the I2CRSR register. The value of reg-
ister I2CRSR<2:1> is compared to the value of the I2CADD<9:8> register. The value of
I2CRSR<7:3> is compared to ‘11110’. The device address is compared on the falling edge of
the eighth clock (SCL). If the addresses match, the following events occur:
1. An ACK
is generated.
2. The D_A and R_W bits are cleared.
3. The module generates the SI2CIF interrupt on the falling edge of the ninth SCL clock.
The module does generate an interrupt after the reception of the first byte of a 10-bit address,
however this interrupt is of little use.
The module will continue to receive the second byte into I2CRSR. This time, I2CRSR<7:0> is
compared to I2CADD<7:0>. If the addresses match, the following events occur:
1. An ACK
is generated.
2. The ADD10 bit is set.
3. The module generates the SI2CIF interrupt on the falling edge of the ninth SCL clock.
4. The module will wait for the master to send data or initiate a Repeated Start condition.
Figure 21-24: 10-bit Address Detection Timing Diagram
Note: Following a Repeated Start condition in 10-bit mode, the slave module only matches
the first 7-bit address, ‘11110 A9 A8 0’.
SCL (Master)
SDA (Master)
SDA (Slave)
SI2CIF Interrupt
2 4 51 3
- Detecting Start bit enables address detection.
1
- Address match of first byte clears D_A bit and causes slave logic to generate ACK
.
2
- Reception of first byte clears R_W bit. Slave logic generates interrupt.
3
- Address match of first and second byte sets ADD10 and causes slave logic to generate ACK
.
4
- Reception of second byte completes 10-bit address. Slave logic generates interrupt.
5
I
2
C Bus State
(S) (D) (D)
(A) (Q)(D)
11110A9A8
R/W
D_A
ADD10
SCLREL
A5A6A7 A4 A3 A2 A1 A0
=0
R_W
(D) (D)
(A)(D)
6
- Bus waiting. Slave ready to receive data.
5