dsPIC30F Family Reference Manual
DS70068C-page 21-36 © 2004 Microchip Technology Inc.
21.7.3.4 General Call Operation
The addressing procedure for the I
2
C bus is such that the first byte after a Start condition usually
determines which slave device the master is addressing. The exception is the general call
address, which can address all devices. When this address is used, all enabled devices should
respond with an Acknowledge. The general call address is one of eight addresses reserved for
specific purposes by the I
2
C protocol. It consists of all ‘0’s with R/W = 0. The general call is
always a slave write operation.
The general call address is recognized when the general call enable bit, GCEN (I2CCON<7>),
is set (see Figure 21-25). Following a Start bit detect, 8 bits are shifted into the I2CRSR and the
address is compared against the I2CADD, and is also compared to the general call address.
If the general call address matches, the following events occur:
1. An ACK
is generated.
2. Slave module will set the GCSTAT bit (I2CSTAT<9>).
3. The D_A and R_W bits are cleared.
4. The module generates the SI2CIF interrupt on the falling edge of the ninth SCL clock.
5. The I2CRSR is transferred to the I2CRCV and the RBF flag bit is set (during the eighth
bit).
6. The module will wait for the master to send data.
When the interrupt is serviced, the cause for the interrupt can be checked by reading the
contents of the GCSTAT bit to determine if the device address was device specific or a general
call address.
Note that general call addresses are 7-bit addresses. If A10M bit is set, configuring the slave
module for 10-bit addresses and GCEN is set, the slave module continues to detect the 7-bit
general call address.
Figure 21-25: General Call Address Detection Timing Diagram (GCEN = 1)
SCL (Master)
SDA (Master)
SDA (Slave)
SI2CIF Interrupt
3 41 2
- Detecting Start bit enables
1
I
2
C Bus State
(S) (D) (D)
(A)(D) (Q)
000 0000
R/W
D_A
I2CRCV
RBF
R_W
address detection.
- All ‘0’s and R/W
= 0 bit indicates
2
general call.
- Address match clears D_A bit
3
and sets GCSTAT.
- R_W bit cleared. Slave generates
4
interrupt.
5
- Bus waiting. Slave ready to
5
receive data.
=0
CGSTAT
Slave generates ACK
.
Address loaded into I2CRCV.
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