Microchip Technology dsPIC30F - Page 551

© 2004 Microchip Technology Inc. DS70068C-page 21-37
Section 21. Inter-Integrated Circuit (I
2
C)
Inter-Integrated
Circuit (I
2
C)
21
21.7.3.5 Receiving All Addresses (IPMI Operation)
Some I
2
C system protocols require a slave to act upon all messages on the bus. For example,
the IPMI (Intelligent Peripheral Management Interface) bus uses I
2
C nodes as message repeat-
ers in a distributed network. To allow a node to repeat all messages, the slave module must
accept all messages, regardless of the device address.
Setting the IPMIEN bit (I2CCON<11>) enables this mode (see Figure 21-26). Regardless of the
state of the I2CADD register and the A10M and GCEN bits, all addresses will be accepted.
Figure 21-26: IPMI Address Detection Timing Diagram (IPMIEN = 1)
21.7.3.6 When an Address is Invalid
If a 7-bit address does not match the contents of I2CADD<6:0>, the slave module will return to
an Idle state and ignore all bus activity until after the Stop condition.
If the first byte of a 10-bit address does not match the contents of I2CADD<9:8>, the slave
module will return to an Idle state and ignore all bus activity until after the Stop condition.
If the first byte of a 10-bit address matches the contents of I2CADD<9:8>, however, the second
byte of the 10-bit address does not match I2CADD<7:0>, the slave module will return to an Idle
state and ignore all bus activity until after the Stop condition.
21.7.4 Receiving Data from a Master Device
When the R/W bit of the device address byte is zero and an address match occurs, the R_W bit
(I2CSTAT<2>) is cleared. The slave module enters a state waiting for data sent by the master.
After the device address byte, the contents of the data byte are defined by the system protocol
and are only received by the slave module.
The slave module shifts 8 bits into the I2CRSR register. On the falling edge of the eighth clock
(SCL), the following events occur:
1. The module begins to generate an ACK
or NACK.
2. The RBF bit is set to indicate received data.
3. The I2CRSR byte is transferred to the I2CRCV register for access by the software.
4. The D_A bit is set.
5. A slave interrupt is generated. Software may check the status of the I2CSTAT register to
determine the cause of the event and then clear the SI2CIF flag.
6. The module will wait for the next data byte.
SCL (Master)
SDA (Master)
SDA (Slave)
SI2CIF Interrupt
2 31
- Detecting Start bit enables
1
I
2
C Bus State
(S) (D) (D)
(A)(D) (Q)
R/W
D_A
I2CRCV
RBF
R_W
address detection.
- Regardless of contents of byte
2
address is matched.
Address match clears D_A bit.
- R_W bit set/clear. Slave generates
3
interrupt.
4
- Bus waiting.
4
Slave generates ACK.
Address loaded into I2CRCV.