dsPIC30F Family Reference Manual
DS70068C-page 21-38 © 2004 Microchip Technology Inc.
21.7.4.1 Acknowledge Generation
Normally, the slave module will Acknowledge all received bytes by sending an ACK
on the ninth
SCL clock. If the receive buffer is overrun, the slave module does not generate this ACK
.
Overrun is indicated if either (or both):
1. The buffer full bit, RBF (I2CSTAT<1>), was set before the transfer was received.
2. The overflow bit, I2COV (I2CSTAT<6>), was set before the transfer was received.
Table 21-3 shows what happens when a data transfer byte is received, given the status of the
RBF and I2COV bits. If the RBF bit is already set when the slave module attempts to transfer to
the I2CRCV, the transfer does not occur but the interrupt is generated and the I2COV bit is set.
If both the RBF and I2COV bits are set, the slave module acts similarly. The shaded cells show
the condition where software did not properly clear the overflow condition.
Reading the I2CRCV clears the RBF bit. The I2COV is cleared by writing to a ‘0’ through
software.
Table 21-3: Data Transfer Received Byte Actions
21.7.4.2 WAIT States During Slave Receptions
When the slave module receives a data byte, the master can potentially begin sending the next
byte immediately. This allows the software controlling the slave module 9 SCL clock periods to
process the previously received byte. If this is not enough time, the slave software may want to
generate a bus WAIT period.
The STREN bit (I2CCON<6>) enables a bus WAIT to occur on slave receptions. When
STREN = 1 at the falling edge of the 9th SCL clock of a received byte, the slave module clears
the SCLREL bit. Clearing the SCLREL bit causes the slave module to pull the SCL line low,
initiating a WAIT. The SCL clock of the master and slave will synchronize, as shown in Section
21.6.2 “Master Clock Synchronization”.
When the software is ready to resume reception, the software sets SCLREL. This causes the
slave module to release the SCL line and the master resumes clocking.
Status Bits as Data
Byte Received Transfer
I2CRSR
→ I2CRCV
Generate
ACK
Generate
SI2CIF Interrupt
(Interrupt occurs
if enabled)
Set
RBF
Set
I2COV
RBF I2COV
00 Yes Yes Yes Yes No change
10 No No Yes No change Yes
11 No No Yes No change Yes
0 1 Yes No Yes Yes No change
Note: Shaded cells show state where the software did not properly clear the overflow condition.
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