© 2004 Microchip Technology Inc. DS70068C-page 21-39
Section 21. Inter-Integrated Circuit (I
2
C)
Inter-Integrated
Circuit (I
2
C)
21
21.7.4.3 Example Messages of Slave Reception
Receiving a slave message is a rather automatic process. The software handling the slave
protocol uses the slave interrupt to synchronize to the events.
When the slave detects the valid address, the associated interrupt will notify the software to
expect a message. On receive data, as each data byte transfers to the I2CRCV register, an
interrupt notifies the software to unload the buffer.
Figure 21-27 shows a simple receive message. Being a 7-bit address message, only one
interrupt occurs for the address bytes. Then, interrupts occur for each of four data bytes.
At an interrupt, the software may monitor the RBF, D_A and R_W bits to determine the condition
of the byte received.
Figure 21-28 shows a similar message using a 10-bit address. In this case, two bytes are
required for the address.
Figure 21-29 shows a case where the software does not respond to the received byte and the
buffer overruns. On reception of the second byte, the module will automatically NACK the master
transmission. Generally, this causes the master to resend the previous byte. The I2COV bit
indicates that the buffer has overrun. The I2CRCV buffer retains the contents of the first byte. On
reception of the third byte, the buffer is still full and again the module will NACK the master. After
this, the software finally reads the buffer. Reading the buffer will clear the RBF bit, however the
I2COV bit remains set. The software must clear the I2COV bit. The next received byte will be
moved to the I2CRCV buffer and the module will respond with a ACK
.
Figure 21-30 highlights clock stretching while receiving data. Note in the previous examples,
STREN = 0 which disables clock stretching on receive messages. In this example, the software
sets STREN to enable clock stretching. When STREN = 1, the module will automatically clock
stretch after each received data byte, allowing the software more time to move the data from the
buffer. Note that if RBF = 1 at the falling edge of the 9th clock, the module will automatically clear
the SCLREL bit and pull the SCL bus line low. As shown with the second received data byte, if
the software can read the buffer and clear the RBF before the falling edge of the 9th clock, the
clock stretching will not occur. The software can also suspend the bus at any time. By clearing
the SCLREL bit, the module will pull the SCL line low after it detects the bus SCL low. The SCL
line will remain low, suspending transactions on the bus until the SCLREL bit is set.
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