Microchip Technology dsPIC30F - Page 557

© 2004 Microchip Technology Inc. DS70068C-page 21-43
Section 21. Inter-Integrated Circuit (I
2
C)
Inter-Integrated
Circuit (I
2
C)
21
Figure 21-30: Slave Message (Write Data to Slave: 7-bit Address; Clock Stretching Enabled; A10M = 0; GCEN = 0; IPMIEN = 0)
1
- Software sets the STREN bit to enable clock stretching.
SCL (Master)
SDA (Master)
SCL (Slave)
SDA (Slave)
I2CTRN
TBF
I2CRCV
RBF
SI2CIF
STREN
1 2 3 4 5 6 7 8
A1A0
9
A
D7D6D5D4D3D2D1D0
1 2 3 4 5 6 7 8 9
W
32
A
5 3 8 3
2
- Slave receives address byte.
3
- Next received byte is message data. Byte moved to I2CRCV register, sets RBF.
6
- Software sets SCLREL bit to release clock.
7
- Slave does not clear SCLREL because RBF = 0 at this time.
A6A5A4A3A2
S P
I2COV
R_W
D_A
D7D6D5D4D3D2D1D0
1 2 3 4 5 6 7 8 9
A
D7D6D5 D3D2D1D0
1 2 3 4 5 6 7 8 9
A
SCLREL
5 9 5
D4
4 6 71
4
- Because RBF = 1 at 9th clock, automatic clock stretch begins.
Slave clears SCLREL bit. Slave pulls SCL line low to stretch clock.
5
- Software reads I2CRCV register. RBF bit clears.
8
- Software may clear SCLREL to cause a clock hold. Module must detect SCL low
9
- Software may set SCLREL to release a clock hold.
before asserting SCL low.