dsPIC30F Family Reference Manual
DS70068C-page 21-44 © 2004 Microchip Technology Inc.
21.7.5 Sending Data to a Master Device
When the R/W bit of the incoming device address byte is one and an address match occurs, the
R_W bit (I2CSTAT<2>) is set. At this point, the master device is expecting the slave to respond
by sending a byte of data. The contents of the byte are defined by the system protocol and are
only transmitted by the slave module.
When the interrupt from the address detection occurs, the software can write a byte to the
I2CTRN register to start the data transmission.
The slave module sets the TBF bit. The eight data bits are shifted out on the falling edge of the
SCL input. This ensures that the SDA signal is valid during the SCL high time. When all eight
bits have been shifted out, the TBF bit will be cleared.
The slave module detects the Acknowledge from the master-receiver on the rising edge of the
ninth SCL clock.
If the SDA line is low indicating an Acknowledge (ACK
), the master is expecting more data and
the message is not complete. The module generates a slave interrupt to signal more data is
requested.
A slave interrupt is generated on the falling edge of the ninth SCL clock. Software must check
the status of the I2CSTAT register and clear the SI2CIF flag.
If the SDA line is high, indicating a Not Acknowledge (NACK), then the data transfer is
complete. The slave module resets and does not generate an interrupt. The slave module will
wait for detection of the next Start bit.
21.7.5.1 WAIT States During Slave Transmissions
During a slave transmission message, the master expects return data immediately after
detection of the valid address with R/W
= 1. Because of this, the slave module will automatically
generate a bus WAIT whenever the slave returns data.
The automatic WAIT occurs at the falling edge of the 9th SCL clock of a valid device address
byte or transmitted byte Acknowledged by the master, indicating expectation of more transmit
data.
The slave module clears the SCLREL bit. Clearing the SCLREL bit causes the slave module to
pull the SCL line low, initiating a WAIT. The SCL clock of the master and slave will synchronize
as shown in Section 21.6.2 “Master Clock Synchronization”.
When the software loads the I2CTRN and is ready to resume transmission, the software sets
SCLREL. This causes the slave module to release the SCL line and the master resumes
clocking.
21.7.5.2 Example Messages of Slave Transmission
Slave transmissions for 7-bit address messages are shown in Figure 21-31. When the address
matches and the R/W bit of the address indicates a slave transmission, the module will
automatically initiate clock stretching by clearing the SCLREL bit and generate an interrupt to
indicate a response byte is required. The software will write the response byte into the I2CTRN
register. As the transmission completes, the master will respond with an Acknowledge. If the
master replies with an ACK, the master expects more data and the module will again clear the
SCLREL bit and generate another interrupt. If the master responds with a NACK, no more data
is required and the module will not stretch the clock nor generate an interrupt.
Slave transmissions for 10-bit address messages require the slave to first recognize a 10-bit
address. Because the master must send two bytes for the address, the R/W bit in the first byte
of the address specifies a write. To change the message to a read, the master will send a
Repeated Start and repeat the first byte of the address with the R/W bit specifying a read. At this
point, the slave transmission begins as shown in Figure 21-32.
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