Microchip Technology dsPIC30F - Page 560

dsPIC30F Family Reference Manual
DS70068C-page 21-46 © 2004 Microchip Technology Inc.
Figure 21-32: Slave Message (Read Data from Slave: 10-bit Address)
1
- Slave recognizes Start event, S and P bits set/clear accordingly.
SCL (Master)
SDA (Master)
SCL (Slave)
SDA (Slave)
I2CTRN
TBF
I2CRCV
RBF
SI2CIF
STREN
1 2 3 4 5 6 7 8 9
A
1 42 7 8
2
- Slave receives first address byte. Write indicated. Slave Acknowledges and
6
- Software writes I2CTRN with response data.
8
- At end of 9th clock, if master sent ACK
, module clears SCLREL to suspend clock.
- Slave recognizes Stop event, S and P bits set/clear accordingly.
S P
ADD10
R_W
D_A
SCLREL
5 6
D7D6D5D4D3D2D1D0
1 2 3 4 5 6 7 8 9
N
3 6 97
7
- Software sets SCLREL to release clock hold. Master resumes clocking and
slave transmits data byte.
Slave generates interrupt.
9
- At end of 9th clock, if master sent NACK, no more data expected. Module does not
suspend clock or generate interrupt.
A7A6A5A4A3A2A1A0
1 2 3 4 5 6 7 8 9
A
A9A8
W1 1 1 1
0
1 2 3 4 5 6 7 8 9
A
A9A8
1 1 1 1
0
D7D6D5D4D3D2D1D0
1 2 3 4 5 6 7 8 9
A
3
- Slave receives address byte. Address matches. Slave Acknowledges and
10
10
4
- Master sends a Repeated Start to redirect the message.
5
- Slave receives resend of first address byte. Read indicated. Slave suspends clock.
R
generates interrupt. generates interrupt.