Microchip Technology dsPIC30F - Page 559

© 2004 Microchip Technology Inc. DS70068C-page 21-45
Section 21. Inter-Integrated Circuit (I
2
C)
Inter-Integrated
Circuit (I
2
C)
21
Figure 21-31: Slave Message (Read Data from Slave: 7-bit Address)
1
- Slave recognizes Start event, S and P bits set/clear accordingly.
SCL (Master)
SDA (Master)
SCL (Slave)
SDA (Slave)
I2CTRN
TBF
I2CRCV
RBF
SI2CIF
STREN
1 2 3 4 5 6 7 8
A1A0
9
A
D7D6D5D4D3D2D1D0
1 2 3 4 5 6 7 8 9
R
1 42
A
5 3 5 3 8
2
- Slave receives address byte. Address matches. Slave generates interrupt.
3
- Software writes I2CTRN with response data. TBF = 1 indicates that buffer is full.
6
- At end of 9th clock, if master sent ACK
, module clears SCLREL to suspend clock.
8
- Slave recognizes Stop event, S and P bits set/clear accordingly.
Address byte not moved to I2CRCV register. R_W = 1 to indicate read from slave. Writing I2CTRN sets D_A, indicating data byte.
A6A5A4A3A2
S P
I2COV
R_W
D_A
SCLREL
4 4
D7D6D5D4D3D2D1D0
1 2 3 4 5 6 7 8 9
A
D7D6D5D4D3D2D1D0
1 2 3 4 5 6 7 8 9
N
3 6 6 5 7
SCLREL = 0 to suspend master clock.
4
- Software sets SCLREL to release clock hold. Master resumes clocking and
slave transmits data byte.
5
- After last bit, module clears TBF bit indicating buffer is available for next byte.
Slave generates interrupt.
7
- At end of 9th clock, if master sent NACK, no more data expected. Module does not
suspend clock and will generate an interrupt.