Microchip Technology dsPIC30F - Page 555

© 2004 Microchip Technology Inc. DS70068C-page 21-41
Section 21. Inter-Integrated Circuit (I
2
C)
Inter-Integrated
Circuit (I
2
C)
21
Figure 21-28: Slave Message (Write Data to Slave: 10-bit Address; Address Matches; A10M=1; GCEN=0; IPMIEN=0)
1
- Slave recognizes Start event, S and P bits set/clear accordingly.
SCL (Master)
SDA (Master)
SCL (Slave)
SDA (Slave)
I2CRCV
RBF
SI2CIF
STREN
1 2 3 4 5 6 7 8
A9A8
9
A
A7A6A5A4A3A2A1A0
1 2 3 4 5 6 7 8 9
W
1 32
A
4 4 4 6
2
- Slave receives address byte. High order address matches.
3
- Slave receives address byte. Low order address matches.
4
- Next received byte is message data. Byte moved to I2CRCV register, sets RBF.
5
- Software reads I2CRCV register. RBF bit clears.
6
- Slave recognizes Stop event, S and P bits set/clear accordingly.
Slave Acknowledges and generates interrupt. Address byte not
Slave Acknowledges and generates interrupt.
S P
I2COV
R_W
D_A
D7D6D5D4D3D2D1D0
1 2 3 4 5 6 7 8 9
A
D7D6D5D4D3D2D1D0
1 2 3 4 5 6 7 8 9
A
D7D6D5D4D3D2D1D0
1 2 3 4 5 6 7 8 9
A
SCLREL
5 5 5
1 1 1 1
0
Slave Acknowledges and generates interrupt. Address byte not moved to I2CRCV register. moved to I2CRCV register.
SI2CIF cleared by user software.