Microchip Technology dsPIC30F - Page 562

dsPIC30F Family Reference Manual
DS70068C-page 21-48 © 2004 Microchip Technology Inc.
21.8.1 Integrated Signal Conditioning
The SCL and SDA pins have an input glitch filter. The I
2
C bus requires this filter in both the
100 kHz and 400 kHz systems.
When operating on a 400 kHz bus, the I
2
C specification requires a slew rate control of the
device pin output. This slew rate control is integrated into the device. If the DISSLW bit
(I2CCON<9>) is cleared, the slew rate control is active. For other bus speeds, the I
2
C
specification does not require slew rate control and DISSLW should be set.
Some system implementations of I
2
C busses require different input levels for VIL(MAX) and
V
IH(MIN).
In a normal I
2
C system:
V
IL(MAX) = lesser of 1.5V and 0.3 VDD
VIH(MIN) = greater of 3.0V and 0.7 VDD
In an SMBus (System Management Bus) system:
V
IL(MAX) = 0.2 VDD
VIH(MIN) = 0.8 VDD
The SMEN bit (I2CCON<8>) controls the input levels. SMEN is set to change the input levels to
SMBus specifications.