© 2004 Microchip Technology Inc. DS70055C-page 8-9
Section 8. Reset
Reset
8
8.7.1 BOR Configuration
The BOR module is enabled/disabled and configured via device configuration fuses.
The BOR module is enabled by default and may be disabled (to reduce power consumption) by
programming the BOREN device configuration fuse to a ‘0’ (FBORPOR<7>). The BOREN
configuration fuse is located in the FBORPOR Device Configuration register. The BOR voltage
trip point (V
BOR) is selected using the BORV<1:0> configuration fuses (FBOR<5:4>). Refer to
Section 24. “Device Configuration” for further details.
8.7.2 Current Consumption for BOR Operation
The BOR circuit relies on an internal voltage reference circuit that is shared with other peripheral
devices, such as the Low Voltage Detect module. The internal voltage reference will be active
whenever one of its associated peripherals is enabled. For this reason, the user may not observe
the expected change in current consumption when the BOR is disabled.
8.7.3 Illegal Opcode Reset
A device Reset will be generated if the device attempts to execute an illegal opcode value that
was fetched from program memory. The Illegal Opcode Reset function can prevent the device
from executing program memory sections that are used to store constant data. To take
advantage of the Illegal Opcode Reset, use only the lower 16 bits of each program memory
section to store the data values. The upper 8 bits should be programmed with 0x3F, which is an
illegal opcode value.
If a device Reset occurs as a result of an illegal opcode value, the IOPUWR status bit
(RCON<14>) will be set.
8.7.4 Uninitialized W Register Reset
The W register array (with the exception of W15) is cleared during all Resets and is considered
uninitialized until written to. An attempt to use an uninitialized register as an address pointer will
reset the device. Furthermore, the IOPUWR status bit (RCON<14>) will be set.
8.7.5 Trap Conflict Reset
A device Reset will occur whenever multiple hard trap sources become pending at the same
time. The TRAPR status bit (RCON<15>) will be set. Refer to Section 6. “Reset Interrupts” for
more information on Trap Conflict Resets.
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