© 2004 Microchip Technology Inc. DS70070B-page 23-59
Section 23. CAN
CAN Module
23
23.8.2 Error Modes and Error Counters
The CAN controller contains the two error counters Receive Error Counter (RERRCNT) and
Transmit Error Counter (TERRCNT). The values of both counters can be read by the CPU from
the Error Count Register CiEC. These counters are incremented or decremented according to
the CAN bus specification.
The CAN controller is error active if both error counters are below the error passive limit of 128.
It is error passive if at least one of the error counters equals or exceeds 128. It goes bus off if the
Transmit Error Counter equals or exceeds the bus off limit of 256. The device remains in this
state, until the bus off recovery sequence is finished, which is 128 consecutive 11 recessive bit
times. Additionally, there is a error state warning flag bit, EWARN (CiINTF<8>), which is set if at
least one of the error counters equals or exceeds the error warning limit of 96. EWARN is reset
if both error counters are less than the error warning limit.
Figure 23-19: Error Modes
23.8.3 Error Flag Register
The values in the error flag register indicate which error(s) caused the error interrupt flag. The
RXnOVR error flags (CiINTF<15> and CiINTF<14>) have a different function than the other error
flag bits in this register. The RXnOVR bits must be cleared in order to clear the ERRIF interrupt
flag. The other error flag bits in this register will cause the ERRIF interrupt flag to become set as
the value of the Transmit and Receive Error Counters crosses a specific threshold. Clearing the
ERRIF interrupt flag in these cases will allow the interrupt service routine to be exited without
recursive interrupt occurring. It may be desirable to disable specific interrupts after they have
occurred once to stop the device from interrupting repeatedly as the Error Counter moves up and
down in the vicinity of a threshold value.
Bus
Off
Error
Active
Error
Passive
RERRCNT > 127 or
TERRCNT > 127
RERRCNT < 127 or
TERRCNT < 127
TERRCNT > 255
128 occurrences of
11 consecutive
“recessive” bits
Reset
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