dsPIC30F Family Reference Manual
DS70070B-page 23-56 © 2004 Microchip Technology Inc.
23.7.8 Transmission Errors
The CAN module will detect the following transmission errors:
• Acknowledge Error
• Form Error
•Bit Error
These transmission errors will not necessarily generate an interrupt but are indicated by the
transmission error counter. However, each of these errors will cause the transmission error
counter to be incremented by one. Once the value of the error counter exceeds the value of 96,
the ERRIF (CiINTF<5>) and the TXWAR bit (CiINTF<10>) are set. Once the value of the error
counter exceeds the value of 96 an interrupt is generated and the TXWAR bit in the error flag
register is set.
A transmission error example is illustrated in Figure 23-18.
Figure 23-18: Error During Transmission
23.7.8.1 Acknowledge Error
In the Acknowledge field of a message, the transmitter checks if the Acknowledge Slot (which it
has sent out as a recessive bit) contains a dominant bit. If not, no other node has received the
frame correctly. An acknowledge error has occurred and the message has to be repeated. No
error frame is generated.
23.7.8.2 Form Error
lf a transmitter detects a dominant bit in one of the four segments including End-Of-Frame,
lnterframe Space, Acknowledge Delimiter or CRC Delimiter; then a form error has occurred and
an error frame is generated. The message is repeated.
23.7.8.3 Bit Error
A bit error occurs if a transmitter sends a dominant bit and detects a recessive bit. In the case
where the transmitter sends a recessive bit and a dominant bit is detected during the Arbitration
field and the Acknowledge Slot, no bit error is generated because normal arbitration is occurring.
1 2
4
5
- Processor sets TXREQ while module inactive. TXERR bit is cleared.
- Module in inactive state. Module begins transmission of queued message.
- Module waits for 11 recessive bits before re-trying transmission of queued message.
- At successful completion of transmission, TXREQ bit cleared and TXnIF bit set.
CAN bus
3
TXREQ
- Module detects error during transmission, releases bus and sets TXERR bit.
CiTX
TXnIF
TXERR
1
2
3
4
5
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