Microchip Technology dsPIC30F - Page 131

© 2004 Microchip Technology Inc. DS70053C-page 6-13
Section 6. Interrupts
Interrupts
6
6.3.3 Returning from Interrupt
The “Return from Interrupt” instruction, RETFIE, exits an interrupt or trap routine.
During the first cycle of a RETFIE instruction, the upper bits of the PC and the SRL register are
popped from the stack. The lower 16 bits of the stacked PC value are popped from the stack
during the second cycle. The third instruction cycle is used to fetch the instruction addressed by
the updated program counter. This cycle executes as a NOP.
Figure 6-6: Return from Interrupt Timing
6.3.4 Special Conditions for Interrupt Latency
The dsPIC30F allows the current instruction to complete when a peripheral interrupt source
becomes pending. The interrupt latency is the same for both one and two-cycle instructions.
However, there are certain conditions that can increase interrupt latency by one cycle, depending
on when the interrupt occurs. The user should avoid these conditions if a fixed latency is critical
to the application. These conditions are as follows:
•A MOV.D instruction is executed that uses PSV to access a value in program memory
space.
• An instruction stall cycle is appended to any two-cycle instruction.
• An instruction stall cycle is appended to any one-cycle instruction that performs a PSV
access.
• A bit test and skip instruction (BTSC, BTSS) uses PSV to access a value in the program
memory space.
4
4
4
4
6
6
CPU
Priority
RETFIE RETFIE PC
INST
Executed
FNOP
ISR last
6
PC + 2
PC + 4
POP Low 16 bits of PC to RAM Stack.
POP SRL and High 8 bits of PC.
PC PC + 2 PC + 4 PC + 6ISR ISR + 2PC
2nd cycle
TCY
instruction