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dsPIC30F Family Reference Manual

6.3.2 Interrupt Latency for Two-Cycle Instructions

The interrupt latency during a two-cycle instruction is the same as during a one-cycle instruction.

The first and second cycle of the interrupt process allow the two-cycle instruction to complete

execution. The timing diagram in Figure 6-5 shows the case when the peripheral interrupt event

occurs in the instruction cycle prior to execution of the two-cycle instruction.

Figure 6-5 shows the timing when a peripheral interrupt is coincident with the first cycle of a

two-cycle instruction. In this case, the interrupt process completes as for a one-cycle instruction

(see Section 6.3.1 ”Interrupt Latency for One-Cycle Instructions”).

Figure 6-4: Interrupt Timing During a Two-Cycle Instruction

Figure 6-5: Interrupt Timing, Interrupt Occurs During 1st Cycle of a 2-Cycle Instruction

466 644

INST(PC-2)

INST(PC)

FNOP ISR

INST

Executed

Interrupt Flag

PUSH Low 16 bits of PC

PUSH SRL and High 8 bits of PC

ISR + 2

ISR + 4

CPU Priority

Fetch

2000 (ISR) 2002 2004 2006PC PC+2PC

Vector

Save PC in

Status bit

Vector#

Peripheral interrupt event

occurs at or before

TCY

2nd cycle1st cycle

temporary

buffer.

midpoint of this cycle.

(from temporary buffer).