Microchip Technology dsPIC30F - Page 344

dsPIC30F Family Reference Manual
DS70062C-page 15-34 © 2004 Microchip Technology Inc.
15.10.5 Fault Pin Software Control
Each of the fault pins can be controlled manually in software. Since each fault input is shared
with a PORT I/O pin, the PORT pin can be configured as an output by clearing the
corresponding TRIS bit. When the PORT bit for the pin is cleared, the fault input will be
activated.
15.10.6 Fault Timing Examples
Figure 15-19: Example Fault Timing, Cycle-by-Cycle Mode
Figure 15-20: Example Fault Timing, Latched Mode
Note: The user should exercise caution when controlling the fault inputs in software. If the
TRIS bit for the fault pin is cleared, then the fault input cannot be driven externally.
PWM
PTMR
FLTA
FLTA
Fault statePWM
Case 2:
Case 1:
Fault state
FLTA
PWM
Case 3:
duty cycle = 50%
duty cycle = 50%
duty cycle = 100%
Fault state
PWM Period
Note: Arrows indicate the time when normal PWM operation is restored.
PWMxx
PTMR
FLTA
Fault state
Duty cycle = 50%
Fault condition ends
Interrupt flag
cleared in
software
Return to
normal
operation
FLTAIF