© 2004 Microchip Technology Inc. DS70062C-page 15-33
Section 15. Motor Control PWM
Motor Control
PWM
15
15.10.2 Fault States
The FLTACON and FLTBCON special function registers each have 8 bits that determine the
state of each PWM I/O pin when the fault input pin becomes active. When these bits are
cleared, the PWM I/O pin will be driven to the inactive state. If the bit is set, the PWM I/O pin will
be driven to the active state. The active and inactive states are referenced to the polarity
defined for each PWM I/O pin (set by HPOL and LPOL device configuration bits).
A special case exists when a PWM module I/O pair is in the Complementary mode and both
pins are programmed to be active on a fault condition. The high-side pin will always have
priority in the Complementary mode so that both I/O pins cannot be driven active
simultaneously.
15.10.3 Fault Input Modes
Each of the fault input pins has two modes of operation:
• Latched Mode: When the fault pin is driven low, the PWM outputs will go to the states
defined in the FLTxCON register. The PWM outputs will remain in this state until the fault
pin is driven high AND the corresponding interrupt flag (FLTxIF) has been cleared in
software. When both of these actions have occurred, the PWM outputs will return to normal
operation at the beginning of the next PWM period or half-period boundary. If the interrupt
flag is cleared before the fault condition ends, the PWM module will wait until the fault pin is
no longer asserted to restore the outputs.
• Cycle-by-Cycle Mode: When the fault input pin is driven low, the PWM outputs will remain
in the defined fault states for as long as the fault pin is held low. After the fault pin is driven
high, the PWM outputs will return to normal operation at the beginning of the following
PWM period (or half-period boundary in center aligned modes).
The operating mode for each fault input pin is selected using the FLTAM and FLTBM control bits
(FLTACON<7> and FLTBCON<7>).
15.10.3.1 Entry Into a Fault Condition
When a fault pin is enabled and driven low, the PWM pins are immediately driven to their
programmed fault states regardless of the values in the PDCx and OVDCON registers. The fault
action has priority over all other PWM control registers.
15.10.3.2 Exit From a Fault Condition
A fault condition must be cleared by the external circuitry driving the fault input pin high and
clearing the fault interrupt flag (Latched mode only). After the fault pin condition has been
cleared, the PWM module will restore the PWM output signals on the next PWM period or
half-period boundary. For edge aligned PWM generation, the PWM outputs will be restored when
PTMR = 0. For center aligned PWM generation, the PWM outputs will be restored when PTMR
= 0 or PTMR = PTPER, whichever event occurs first.
An exception to these rules will occur when the PWM time base is disabled (PTEN = 0). If the
PWM time base is disabled, the PWM module will restore the PWM output signals immediately
after the fault condition has been cleared.
15.10.4 Fault Pin Priority
If both fault input pins have been assigned to control a particular pair of PWM pins, the fault
states programmed for the FLTA
input pin will take priority over the FLTB input pin.
One of two actions will take place when the Fault A condition has been cleared. If the FLTB
input is still asserted, the PWM outputs will return to the states programmed in the FLTBCON
register on the next period or half-period boundary. If the FLTB
input is not asserted, the PWM
outputs will return to normal operation on the next period or half-period boundary.
Note: When the FLTA pin is programmed for Latched mode, the PWM outputs will not
return to the Fault B states or normal operation until the Fault A interrupt flag has
been cleared and the FLTA
pin is de-asserted.
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