© 2004 Microchip Technology Inc. DS70066C-page 19-17
Section 19. UART
UART
19
19.6.4 Setup for UART Reception
Steps to follow when setting up a Reception:
1. Initialize the UxBRG register for the appropriate baud rate (Section 19.3 “UART Baud
Rate Generator (BRG)”).
2. Set the number of data bits, number of Stop bits and parity selection by writing to the
PDSEL<1:0> (UxMODE<2:1>) and STSEL (UxMODE<0>) bits.
3. If interrupts are desired, then set the UxRXIE bit in the corresponding Interrupt Enable
Control register (IEC). Specify the interrupt priority for the interrupt using the
UxRXIP<2:0> control bits in the corresponding Interrupt Priority Control register (IPC).
Also, select the Receive Interrupt mode by writing to the URXISEL<1:0> (UxSTA<7:6>)
bits.
4. Enable the UART module by setting the UARTEN (UxMODE<15>) bit.
5. Receive interrupts will depend on the URXISEL<1:0> control bit settings. If receive
interrupts are not enabled, the user can poll the URXDA bit. The UxRXIF bit should be
cleared in the software routine that services the UART receive interrupt.
6. Read data from the receive buffer. If 9-bit transmission has been selected, read a word.
Otherwise, read a byte. The URXDA status bit (UxSTA<0>) will be set whenever data is
available in the buffer.
Figure 19-6: UART Reception
Figure 19-7: UART Reception with Receive Overrun
Start
bit
bit1bit0
bit7 bit0Stop
bit
Start
bit bit7
Stop
bit
UxRX
RIDLE bit
Character 1
to UxRXREG
Character 2
to UxRXREG
Note: This timing diagram shows 2 characters received on the UxRX input.
UxRXIF
(URXISEL = 0x)
Start
bit
bit7/8
bit1bit0
bit7/8 bit0Stop
bit
Start
bit
Start
bit
bit7/8
Stop
bit
UxRX
OERR bit
RIDLE bit
Character 1,2,3,4
stored in Receive
Character 5
held in UxRSR
Stop
bit
Character 1 Characters 2,3,4,5 Character 6
FIFO
OERR Cleared by User
Note: This diagram shows 6 characters received without the user reading the input buffer. The 5th character received is held in the
receive shift register. An overrun error occurs at the start of the 6th character.
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