Microchip Technology dsPIC30F - Page 480

dsPIC30F Family Reference Manual
DS70066C-page 19-16 © 2004 Microchip Technology Inc.
Figure 19-5: UART Receiver Block Diagram
URX8 UxRXREG Low Byte
Load RSR
UxMODE
Receive Buffer Control
– Generate Flags
– Generate Interrupt
UxRXIF
UxRX
· START bit Detect
Receive Shift Register
16 Divider
Control
Signals
16X Baud Clock
from Baud Rate
Generator
UxSTA
– Shift Data Characters
to Buffer
9
(UxRSR)
PERR
FERR
· Parity Check
· Stop bit Detect
· Shift Clock Generation
· Wake Logic
16
Internal Data Bus
1
0
LPBACK
From UxTX
15
9
8
7
0
Word Read Only
Word or
Byte Read