Microchip Technology dsPIC30F - Page 476

dsPIC30F Family Reference Manual
DS70066C-page 19-12 © 2004 Microchip Technology Inc.
19.5.1 Transmit Buffer (UxTXB)
Each UART has a 4-deep, 9-bit wide FIFO transmit data buffer. The UxTXREG register provides
user access to the next available buffer location. The user may write up to 4 words in the buffer.
Once the UxTXREG contents are transferred to the UxTSR register, the current buffer location
becomes available for new data to be written and the next buffer location is sourced to the UxTSR
register. The UTXBF (UxSTA<9>) status bit is set whenever the buffer is full. If a user attempts
to write to a full buffer, the new data will not be accepted into the FIFO.
The FIFO is reset during any device Reset, but is not affected when the device enters a Power
Saving mode or wakes up from a Power Saving mode.
19.5.2 Transmit Interrupt
The transmit interrupt flag (UxTXIF) is located in the corresponding interrupt flag status (IFS)
register. The UTXISEL control bit (UxSTA<15>) determines when the UART will generate a
transmit interrupt.
1. If UTXISEL = 0, an interrupt is generated when a word is transferred from the transmit
buffer to the Transmit Shift register (UxTSR). This implies that the transmit buffer has at
least one empty word. Since an interrupt is generated after the transfer of each individual
word, this mode is useful if interrupts can be handled frequently (i.e., the ISR is completed
before the transmission of the next word).
2. If UTXISEL = 1, an interrupt is generated when a word is transferred from the transmit
buffer to the Transmit Shift register (UxTSR) and the transmit buffer is empty. Since an
interrupt is generated only after all 4 words have been transmitted, this ‘Block Transmit’
mode is useful if the user’s code cannot handle interrupts quickly enough (i.e., the ISR is
completed before the transmission of the next word).
The UxTXIF bit will be set when the module is first enabled.
The user should clear the UxTXIF bit in the ISR.
Switching between the two Interrupt modes during operation is possible.
While the UxTXIF flag bit indicates the status of the UxTXREG register, the TRMT bit
(UxSTA<8>) shows the status of the UxTSR register. The TRMT status bit is a read only bit,
which is set when the UxTSR register is empty. No interrupt logic is tied to this bit, so the user
has to poll this bit in order to determine if the UxTSR register is empty.
Note: When the UTXEN bit is set, the UxTXIF flag bit will also be set if UTXISEL = 0, since
the transmit buffer is not yet full (can move transmit data to the UxTXREG register).