© 2004 Microchip Technology Inc. DS70069C-page 22-27
Section 22. Data Converter Interface (DCI)
Data Converter
Interface (DCI)
22
22.5.6.2 16-bit AC-Link Mode
In the 16-bit AC-Link mode, transmit and receive data word lengths are restricted to 16 bits to fit
the DCI Transmit and Receive registers. Note that this restriction only affects the 20-bit data time
slots of the AC-Link protocol. For received time slots, the incoming data will be truncated to 16
bits. For outgoing time slots, the 4 LSbs of the data word are set to ‘0’ by the module. This
Operating mode simplifies the AC-Link data frame by treating every time slot as a 16-bit time slot.
The frame sync generator maintains alignment to the time slot boundaries.
22.5.6.3 20-bit AC-Link Mode
The 20-bit AC-Link mode allows all bits in the data time slots to be transmitted and received, but
does not maintain data alignment to the specific time slot boundaries defined in the AC-Link
protocol.
The 20-bit AC-Link mode functions similarly to the Multi-Channel mode of the DCI module,
except for the duty cycle of the frame synchronization signal that is produced. The AC-Link frame
synchronization signal should remain high for 16 clock cycles and should be low for the following
240 cycles.
The 20-bit mode treats each 256-bit AC-Link frame as sixteen 16-bit time slots. In the 20-bit
AC-Link mode, the module operates as if COFSG<3:0> = 1111b and WS<3:0> = 1111b. The
data alignment for 20-bit data slots is not maintained in this Operating mode. For example, an
entire 256-bit AC-Link data frame can be transmitted and received in a packed fashion by setting
all bits in the TSCON and RSCON registers. Since the total available buffer length is 64 bits, it
would take 4 consecutive interrupts to transfer the AC-Link frame. The application software must
keep track of the current AC-Link frame segment by monitoring the SLOT<3:0> status bits
(DCISTAT<11:7>).
22.5.6.4 AC-Link Setup Details
The module is enabled for AC-Link mode by writing 10h or 11h to the COFSM<1:0> control bits
in the DCICON1 SFR. The word size selection bits (WS<3:0>) and the frame synchronization
generator bits (COFSG<3:0>) have no effect for the 16 and 20-bit AC-Link modes since the
frame and word sizes are set by the protocol.
Most AC ‘97 codecs generate the clock signal that controls data transfers. Therefore, the CSCKD
control bit is set in software. The COFSD control bit is cleared because the DCI will generate the
FS signal from the incoming clock signal. The CSCKE bit is cleared so that data is sampled on
the rising edge.
The user must decide which time slots in the AC-Link data frame are to be buffered and set the
TSE and RSE control bits accordingly. At a minimum, it will be necessary to buffer the transmit
and receive TAG slots, so the TSCON<0> and RSCON<1> control bits should be set in software.
1. The DCI must be configured to accept the serial transfer clock from the AC ’97 codec. Set
the CSCKD control bit and clear the DCICON3 register.
2. Next, set the COFSM<1:0> control bits (DCICON1<1:0>) to 10b or 11b to set the desired
AC-Link Frame Synchronization mode.
3. Clear the COFSD control bit (DCICON1<8>), so the DCI will output the frame sync signal.
4. Clear the CSCKE control bit (DCICON1<9>) to sample incoming data on the falling edge
of CSCK.
Note: Only the TSCON<12:0> control bits and the RSCON<12:0> control bits will have an
effect in the 16-bit AC-Link mode, since an AC-Link frame has 13 time slots.
Note: The word size selection bits (WS<3:0>) and the frame synchronization generator
bits (COFSG<3:0>) have no effect for the 16- and 20-bit AC-Link modes, since the
frame and word sizes are set by the protocol.
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