Microchip Technology dsPIC30F - Page 530

dsPIC30F Family Reference Manual
DS70068C-page 21-16 © 2004 Microchip Technology Inc.
21.5.1 Generating Start Bus Event
To initiate a Start event, the software sets the Start enable bit, SEN (I2CCON<0>). Prior to
setting the Start bit, the software can check the P (I2CSTAT<4>) status bit to ensure that the bus
is in an Idle state.
Figure 21-8 shows the timing of the Start condition.
• Slave logic detects the Start condition sets the S bit (I2CSTAT<3>) and clears the P bit
(I2CSTAT<4>).
• SEN bit is automatically cleared at completion of the Start condition.
• MI2CIF interrupt generated at completion of the Start condition.
• After Start condition, SDA line and SCL line are left low (Q state).
21.5.1.1 IWCOL Status Flag
If the software writes the I2CTRN when a Start sequence is in progress, then IWCOL is set and
the contents of the transmit buffer are unchanged (the write doesn’t occur).
Figure 21-8: Master Start Timing Diagram
Note: Because queueing of events is not allowed, writing to the lower 5 bits of I2CCON is
disabled until the Start condition is complete.
SCL (Master)
SDA (Master)
S
SEN
MI2CIF Interrupt
TBRG
1 2 3 4
- Writing SEN = 1 initiates a master Start event.
1
TBRG
Baud generator starts.
- Baud generator times out. Master module drives SDA low.
2
Baud generator restarts.
- Slave module detects Start, sets S = 1, P = 0.
3
- Baud generator times out. Master module drives SCL low,
4
generates interrupt and clears SEN.
I
2
C Bus State
(I) (S) (Q)
P