© 2004 Microchip Technology Inc. DS70068C-page 21-17
Section 21. Inter-Integrated Circuit (I
2
C)
Inter-Integrated
Circuit (I
2
C)
21
21.5.2 Sending Data to a Slave Device
Transmission of a data byte, a 7-bit device address byte or the second byte of a 10-bit address,
is accomplished by simply writing the appropriate value to the I2CTRN register. Loading this
register will start the following process:
• The software loads the I2CTRN with the data byte to transmit.
• Writing I2CTRN sets the buffer full flag bit, TBF (I2CSTAT<0>).
• The data byte is shifted out the SDA pin until all 8 bits are transmitted. Each bit of
address/data will be shifted out onto the SDA pin after the falling edge of SCL.
• On the ninth SCL clock, the module shifts in the ACK bit from the slave device and writes its
value into the ACKSTAT bit (I2CCON<15>).
• The module generates the MI2CIF interrupt at the end of the ninth SCL clock cycle.
Note that the module does not generate or validate the data bytes. The contents and usage of
the byte is dependant on the state of the message protocol maintained by the software.
21.5.2.1 Sending a 7-bit Address to the Slave
Sending a 7-bit device address involves sending 1 byte to the slave. A 7-bit address byte must
contain the 7 bits of I
2
C device address and a R/W bit that defines if the message will be a write
to the slave (master transmission and slave receiver) or a read from the slave (slave transmission
and master receiver).
21.5.2.2 Sending a 10-bit Address to the Slave
Sending a 10-bit device address involves sending 2 bytes to the slave. The first byte contains 5
bits of I
2
C device address reserved for 10-bit Addressing modes and 2 bits of the 10-bit address.
Because the next byte, which contains the remaining 8 bits of the 10-bit address must be
received by the slave, the R/W
bit in the first byte must be ‘0’, indicating master transmission and
slave reception. If the message data is also directed toward the slave, the master can continue
sending the data. However, if the master expects a reply from the slave, a Repeated Start
sequence with the R/W
bit at ‘1’ will change the R/W state of the message to a read of the slave.
21.5.2.3 Receiving Acknowledge from the Slave
On the falling edge of the eighth SCL clock, the TBF bit is cleared and the master will de-assert
the SDA pin allowing the slave to respond with an Acknowledge. The master will then generate
a ninth SCL clock.
This allows the slave device being addressed to respond with an ACK
bit during the ninth
bit time if an address match occurs, or if data was received properly. A slave sends an
Acknowledge when it has recognized its device address (including a general call), or when the
slave has properly received its data.
The status of ACK
is written into the Acknowledge status bit, ACKSTAT (I2CSTAT<15>), on the
falling edge of the ninth SCL clock. After the ninth SCL clock, the module generates the MI2CIF
interrupt and enters an Idle state until the next data byte is loaded into I2CTRN.
21.5.2.4 ACKSTAT Status Flag
The ACKSTAT bit (I2CCON<15>) is cleared when the slave has sent an Acknowledge
(ACK
= 0), and is set when the slave does not Acknowledge (ACK = 1).
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