dsPIC30F Family Reference Manual
DS70068C-page 21-18 © 2004 Microchip Technology Inc.
21.5.2.5 TBF Status Flag
When transmitting, the TBF bit (I2CSTAT<0>) is set when the CPU writes to I2CTRN and is
cleared when all 8 bits are shifted out.
21.5.2.6 IWCOL Status Flag
If the software writes the I2CTRN when a transmit is already in progress (i.e., the module is still
shifting out a data byte), then IWCOL is set and the contents of the buffer are unchanged (the
write doesn’t occur). IWCOL must be cleared in software.
Figure 21-9: Master Transmission Timing Diagram
Note: Because queueing of events is not allowed, writing to the lower 5 bits of I2CCON is
disabled until the transmit condition is complete.
D7 D6 D5 D4 D3 D2 D1 D0
SCL (Master)
SCL (Slave)
SDA (Master)
SDA (Slave)
TBF
I2CTRN
MI2CIF Interrupt
TBRG TBRG
5 6 7 81 2 3 4
- Writing the I2CTRN register will start a master transmission event. TBF bit is set.
1
- Baud generator starts. The MSB of the I2CTRN drives SDA. SCL remains low. TRSTAT bit is set.
2
- Baud generator times out. SCL released. Baud generator restarts.
3
- Baud generator times out. SCL driven low. After SCL detected low, next bit of I2CTRN drives SDA.
4
- While SCL is low, the slave can also pull SCL low to initiate a WAIT (clock stretch).
5
- Master has already released SCL, and slave can release to end WAIT. Baud generator restarts.
6
- At falling edge of 8th SCL clock, master releases SDA. TBF bit is cleared. Slave drives ACK/NACK.
7
- At falling edge of 9th SCL clock, master generates interrupt. SCL remains low until next event.
8
Slave releases SDA. TRSTAT bit is clear.
I
2
C Bus State
(Q) (D) (Q)
(A) (Q)(D) (Q)
TRSTAT
ACKSTAT
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