© 2004 Microchip Technology Inc. DS70068C-page 21-19
Section 21. Inter-Integrated Circuit (I
2
C)
Inter-Integrated
Circuit (I
2
C)
21
21.5.3 Receiving Data from a Slave Device
Setting the receive enable bit, RCEN (I2CCON<3>), enables the master to receive data from a
slave device.
The master logic begins to generate clocks and before each falling edge of the SCL, SDA line is
sampled and data is shifted into the I2CRSR.
After the falling edge of the eighth SCL clock:
• The RCEN bit is automatically cleared.
• The contents of the I2CRSR transfer into the I2CRCV.
• The RBF flag bit is set.
• The module generates the MI2CIF interrupt.
When the CPU reads the buffer, the RBF flag bit is automatically cleared. The software can
process the data and then do an Acknowledge sequence.
21.5.3.1 RBF Status Flag
When receiving data, the RBF bit is set when an device address or data byte is loaded into
I2CRCV from I2CRSR. It is cleared when software reads the I2CRCV register.
21.5.3.2 I2COV Status Flag
If another byte is received in the I2CRSR while the RBF bit remains set and the previous byte
remains in the I2CRCV register, the I2COV bit is set and the data in the I2CRSR is lost.
Leaving I2COV set does not inhibit further reception. If RBF is cleared by reading the I2CRCV,
and the I2CRSR receives another byte, that byte will be transferred to the I2CRCV.
21.5.3.3 IWCOL Status Flag
If the software writes the I2CTRN when a receive is already in progress (i.e., I2CRSR is still
shifting in a data byte), then the IWCOL bit is set and the contents of the buffer are unchanged
(the write doesn’t occur).
Note: The lower 5 bits of I2CCON must be ‘0’ before attempting to set the RCEN bit. This
ensures the master logic is inactive.
Note: Since queueing of events is not allowed, writing to the lower 5 bits of I2CCON is
disabled until the data reception condition is complete.
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