dsPIC30F Family Reference Manual
DS70068C-page 21-20 © 2004 Microchip Technology Inc.
Figure 21-10: Master Reception Timing Diagram
D7 D6 D5
D4 D3
D2
D1 D0
SCL (Master)
SCL (Slave)
SDA (Slave)
SDA (Master)
RBF
I2C Bus State
MI2CIF Interrupt
TBRG
5 62 3 4
- Writing the RCEN bit will start a master reception event. The baud generator starts. SCL remains low.
2
- Baud generator times out. Master attempts to release SCL.
3
- When slave releases SCL, baud generator restarts.
4
- Baud generator times out. MSB of response shifted to I2CRSR. SCL driven low for next baud interval.
5
- At falling edge of 8th SCL clock, I2CRSR transferred to I2CRCV. Module clears RCEN bit.
6
TBRG
RCEN
(Q) (D) (Q) (Q)(D)(Q)
I2CRCV
RBF bit is set. Master generates interrupt.
(Q)
1
- Typically, the slave can pull SCL low (clock stretch) to request a wait to prepare data response.
1
The slave will drive MSB of data response on SDA when ready.
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