© 2004 Microchip Technology Inc. DS70068C-page 21-5
Section 21. Inter-Integrated Circuit (I
2
C)
Inter-Integrated
Circuit (I
2
C)
21
21.2.1 Bus Protocol
The following I2C bus protocol has been defined:
• Data transfer may be initiated only when the bus is not busy.
• During data transfer, the data line must remain stable whenever the SCL clock line is HIGH.
Changes in the data line while the SCL clock line is HIGH will be interpreted as a Start or
Stop condition.
Accordingly, the following bus conditions have been defined (Figure 21-3).
21.2.1.1 Start Data Transfer (S)
After a bus Idle state, a HIGH-to-LOW transition of the SDA line while the clock (SCL) is HIGH
determines a Start condition. All data transfers must be preceded by a Start condition.
21.2.1.2 Stop Data Transfer (P)
A LOW-to-HIGH transition of the SDA line while the clock (SCL) is HIGH determines a Stop
condition. All data transfers must end with a Stop condition.
21.2.1.3 Repeated Start (R)
After a WAIT state, a HIGH-to-LOW transition of the SDA line while the clock (SCL) is HIGH
determines a Repeated Start condition. Repeated Starts allow a master to change bus direction
without relinquishing control of the bus.
21.2.1.4 Data Valid (D)
The state of the SDA line represents valid data when, after a Start condition, the SDA line is
stable for the duration of the HIGH period of the clock signal. There is one bit of data per SCL
clock.
21.2.1.5 Acknowledge (A) or Not-Acknowledge (N)
All data byte transmissions must be Acknowledged (ACK) or Not Acknowledged (NACK) by the
receiver. The receiver will pull the SDA line low for an ACK or release the SDA line for a NACK.
The Acknowledge is a one-bit period, using one SCL clock.
21.2.1.6 WAIT/Data Invalid (Q)
The data on the line must be changed during the LOW period of the clock signal. Devices may
also stretch the clock low time, by asserting a low on SCL line, causing a WAIT on the bus.
21.2.1.7 Bus Idle (I)
Both data and clock lines remain HIGH at those times after a Stop condition and before a Start
condition.
Figure 21-3: I
2
C Bus Protocol States
Address
Valid
Data
Allowed
to Change
Stop
Condition
Start
Condition
SCL
SDA
(I) (S) (D) (A) or (N) (P) (I)
Data or
(Q)
ACK/NACK
Valid
NACK
ACK
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