dsPIC30F Family Reference Manual
DS70068C-page 21-8 © 2004 Microchip Technology Inc.
Register 21-2 and Register 21-2 define the I
2
C module Control and Status registers, I2CCON
and I2CSTAT.
The I2CTRN is the register to which transmit data is written. This register is used when the
module operates as a master transmitting data to the slave or as a slave sending reply data to
the master. As the message progresses, the I2CTRN register shifts out the individual bits.
Because of this, the I2CTRN may not be written to unless the bus is Idle. The I2CTRN may be
reloaded while the current data is transmitting.
Data being received by either the master or the slave is shifted into a non-accessible Shift
register called I2CRSR. When a complete byte is received, the byte transfers to the I2CRCV
register. In receive operations, the I2CRSR and I2CRCV create a double-buffered receiver. This
allows reception of the next byte to begin before reading the current byte of received data.
If the module receives another complete byte before the software reads the previous byte from
the I2CRCV register, a receiver overflow occurs and sets the I2COV (I2CCON<6>). The byte in
the I2CRSR is lost.
The I2CADD register holds the slave device address. In 10-bit mode, all bits are relevant. In
7-bit addressing mode, only I2CADD<6:0> are relevant. The A10M (I2CCON<10>) specifies the
expected mode of the slave address.
To Next Page
Loading...
