© 2004 Microchip Technology Inc. DS70068C-page 21-9
Section 21. Inter-Integrated Circuit (I
2
C)
Inter-Integrated
Circuit (I
2
C)
21
Register 21-2: I2CCON: I
2
C Control Register
Upper Byte:
R/W-0 U-0 R/W-0 R/W-1
HC
R/W-0 R/W-0 R/W-0 R/W-0
I2CEN — I2CSIDL SCLREL IPMIEN A10M DISSLW SMEN
bit 15 bit 8
Lower Byte:
R/W-0 R/W-0 R/W-0 R/W-0
HC
R/W-0
HC
R/W-0
HC
R/W-0
HC
R/W-0
HC
GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN
bit 7 bit 0
bit 15 I2CEN: I
2
C Enable bit
1 = Enables the I
2
C module and configures the SDA and SCL pins as serial port pins
0 = Disables I
2
C module. All I
2
C pins are controlled by port functions.
bit 14 Unimplemented: Read as ‘0’
bit 13 I2CSIDL: Stop in Idle Mode bit
1 = Discontinue module operation when device enters an Idle mode
0 = Continue module operation in Idle mode
bit 12 SCLREL: SCL Release Control bit (when operating as I
2
C Slave)
1 = Release SCL clock
0 = Hold SCL clock low (clock stretch)
If STREN = 1:
Bit is R/W (i.e., software may write ‘0’ to initiate stretch and write ‘1’ to release clock)
Hardware clear at beginning of slave transmission.
Hardware clear at end of slave reception.
If STREN = 0:
Bit is R/S (i.e., software may only write ‘1’ to release clock)
Hardware clear at beginning of slave transmission.
bit 11 IPMIEN: Intelligent Peripheral Management Interface (IPMI) Enable bit
1 = Enable IPMI Support mode. All addresses Acknowledged.
0 = IPMI mode not enabled
bit 10 A10M: 10-bit Slave Address bit
1 = I2CADD is a 10-bit slave address
0 = I2CADD is a 7-bit slave address
bit 9 DISSLW: Disable Slew Rate Control bit
1 = Slew rate control disabled
0 = Slew rate control enabled
bit 8 SMEN: SMBus Input Levels bit
1 = Enable I/O pin thresholds compliant with SMBus specification
0 = Disable SMBus input thresholds
bit 7 GCEN: General Call Enable bit (when operating as I
2
C slave)
1 = Enable interrupt when a general call address is received in the I2CRSR
(module is enabled for reception)
0 = General call address disabled
bit 6 STREN: SCL Clock Stretch Enable bit (when operating as I
2
C slave)
Used in conjunction with SCLREL bit.
1 = Enable software or receive clock stretching
0 = Disable software or receive clock stretching
bit 5 ACKDT: Acknowledge Data bit (When operating as I
2
C Master. Applicable during master receive.)
Value that will be transmitted when the software initiates an Acknowledge sequence.
1 = Send NACK during acknowledge
0 = Send ACK during acknowledge
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