Microchip Technology dsPIC30F - Page 524

dsPIC30F Family Reference Manual
DS70068C-page 21-10 © 2004 Microchip Technology Inc.
Register 21-1: I2CCON: I
2
C Control Register (Continued)
bit 4 ACKEN: Acknowledge Sequence Enable bit
(When operating as I
2
C master. Applicable during master receive.)
1 = Initiate Acknowledge sequence on SDA and SCL pins, and transmit ACKDT data bit
Hardware clear at end of master Acknowledge sequence.
0 = Acknowledge sequence not in progress
bit 3 RCEN: Receive Enable bit (when operating as I
2
C master)
1 = Enables Receive mode for I
2
C
Hardware clear at end eighth bit of master receive data byte.
0 = Receive sequence not in progress
bit 2 PEN: Stop Condition Enable bit (when operating as I
2
C master)
1 = Initiate Stop condition on SDA and SCL pins
Hardware clear at end of master Stop sequence.
0 = Stop condition not in progress
bit 1 RSEN: Repeated Start Condition Enabled bit (when operating as I
2
C master)
1 = Initiate Repeated Start condition on SDA and SCL pins
Hardware clear at end of master Repeated Start sequence.
0 = Repeated Start condition not in progress
bit 0 SEN: Start Condition Enabled bit (when operating as I
2
C master)
1 = Initiate Start condition on SDA and SCL pins
Hardware clear at end of master Start sequence.
0 = Start condition not in progress
Legend:
R = Readable C = Clearable bit U = Unimplemented bit, read as ‘0’
W = Writable HS = Set by Hardware S = Settable bit
HC = Cleared by Hardware ‘0’ = Bit cleared at POR x = Bit is unknown at POR
‘1’ = Bit is set at POR