3
Introduction
The SmartFusion2 MSS has an embedded DDR controller. This DDR controller is intended to control an
off-chip DDR memory. The MDDR controller can be accessed from the MSS as well as from the FPGA
fabric. In addition, the DDR controller can also be bypassed, providing an additional interface to the
FPGA fabric (Soft Controller Mode (SMC)).
To fully configure the MSS DDR controller, you must:
1. Select the datapath using the MDDR Configurator.
2. Set the register values for the DDR controller registers.
3. Select the DDR memory clock frequencies and FPGA fabric to MDDR clock ratio (if needed)
using the MSS CCC Configurator.
4. Connect the controller’s APB configuration interface as defined by the Peripheral Initialization
solution. For the MDDR Initialization circuitry built by System Builder, refer to the "MSS DDR
Configuration Path" on page 13 and Figure 2-7.
You can also build your own initialization circuitry using standalone (not by System Builder)
Peripheral Initialization. Refer to the SmartFusion2 Standalone Peripheral Initialization User
Guide.
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