13
P_SCLR_N Input Synchronous reset for result P, CDOUT, Overflow/Carryout registers
P_EN Input Enable for result P, CDOUT, Overflow/Carryout registers
P Output Pn = Pn-1 + CARRYIN + C + (A0 * B0) + (A1*B1)
OVERFLOW Output When high, indicates that the result exceeded the width of output P.
OVERFLOW = (P[36] ^ P[35]) | (P[35] ^ P[34])
CARRYOUT Output This bit can be used to extend the adder in the fabric.
CARRYOUT = C[34] ^ D[34] ^ P[35]
CDOUT Output
Cascade
Cascade output of result P. CDOUT is a sign-extended copy of P. The entire bus
must either be dangling or drive an entire CDIN of another MATH block in Dot
Product mode.
Table 3-2 • Hard Multiplier Accumulator Ports - Dot Product Mode (continued)
Signal Direction Description
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