Microsemi SmartFusion2 - Page 12

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Table 3-2 lists the Hard Multiplier Accumulator port signals for Dot Product mode.
CARRYOUT Output This bit can be used to extend the adder in the fabric.
CARRYOUT = C[43] ^ D[43] ^ P[44]
CDOUT Output
Cascade
Cascade output of result P. CDOUT is a copy of P, sign-extended to 44
bits. The entire bus must either be dangling or drive an entire CDIN of
another MATH block in Normal mode.
Table 3-1 • Hard Multiplier Accumulator Ports - Normal Mode (continued)
Signal Direction Description
Table 3-2 • Hard Multiplier Accumulator Ports - Dot Product Mode
Signal Direction Description
A0 Input Input data A0, 2- 9 bits wide
B0 Input Input data B0, 2- 9 bits wide
A1 Input Input data A1, 2- 9 bits wide
B1 Input Input data B1, 2- 9 bits wide
C Input Input data C, 2- 35 bits wide
CLK Input Input clock for all registers
A0_ACLR_N Input Asynchronous reset for data A0 registers
A0_SCLR_N Input Synchronous reset for data A0 registers
A0_EN Input Enable for data A0 registers
B0_ACLR_N Input Asynchronous reset for data B0 registers
B0_SCLR_N Input Synchronous reset for data B0 registers
B0_EN Input Enable for data B0 registers
A1_ACLR_N Input Asynchronous reset for data A1 registers
A1_SCLR_N Input Synchronous reset for data A1 registers
A1_EN Input Enable for data A1 registers
B1_ACLR_N Input Asynchronous reset for data B1 registers
B1_SCLR_N Input Synchronous reset for data B1 registers
B1_EN Input Enable for data B1 registers
C_ACLR_N Input Asynchronous reset for data C, Carry In registers
C_SCLR_N Input Synchronous reset for data C, Carry In registers
C_EN Input Enable for data C, Carry In registers
CARRYIN Input Carry In input for operand C
P_ACLR_N Input Asynchronous reset for result P, CDOUT, Overflow/Carryout registers