9.
COMMUNICATIONS
IN
THE NO-PROTOCOL
MODE
MELSEGA
(5)
Clearing the receive buffer memory
If and error occurs due to failure of
an
external device, for example,
while receiving data from an external device
in
the
no-protocol mode,
the data received
up
to the error may be incorrect or interrupted. To
received up to the error may be incorrect or interrupted. To recover
after an error has occurred
it
is possible to cleaa all received data and
initialized the AJ71 C24 buffer memory.
(a) Error detection
The following methods are used to detect errors while data is being
received.
1) Reading the error LED display area
To detect errors the PC CPU can read the LED
ON/OFF
statuses,
stored at buffer memory address 101H as transmission error
data.
2)
PC
input signals
Signals such as READY signals from external devices are con-
nected to the PC CPU as
input
signals. The PC CPU can detect
errors from the
ON/OFF
status of these signals.
(b) Clearing received data
Range of data cleared
All
data already received by the AJ71C24 is cleared and the
no-prptocol mode receive buffer memory area is initialized (See
Section
3.5.2
and
3.5.3
for details).
How to clear received data
Received data is cleared by writing "1" to buffer memory address
lODH using the
[TO]
instruction.
After clearing received data, the AJ71C24 clears the "1" that was
written to buffer memory address IODH.
The received data may be cleared
while
the receive data read
request signal (Xnl) and received data read completed signal
(Y(n+l)l) are
OFF.
Use
Xnl
and Y(n+l)l as an interlock for TO instruction.
AJ71
C24
Addre?q
1
ODH
Address 1
ODn
\
IrOI
i-
(Write
'1
"
to buffer
memory
address
lob)
I
u
9-
14
Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com
To Next Page
Loading...
