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3.
SPECIFICATIONS
MELSEC-A
3.5.2
DTR
/DSR
(EWDR)
control
This appendix explains DTR/DSR (ER/DR) control.
(1)
Explanation of DTR/DSR control
DTR/DSR control enables and disables data communications with an
external device via the
AJ71C24 RS-232C
by means of the DSR (DR)
and DTR
(ER)
signals.
DTR/DSR control is not available for the
RS-422.
(2)
Receive data flow
Data received from an external device is stored in the
AJ71C24
no-
protocol receive buffer memory area via the
OS
memory area.
Under the following conditions, the
AJ71C24
temporarily stores
received data to its
OS
area. When transfer to the no-protocol receive
buffer memory is enabled (read request signal
Xnl
is
OFF),
data is
transferred until the receive completed code is received, or until the
fixed length
of
data has been transmitted.
Conditions:
1)
When there is too much data for the buffer memory because the
received data length exceeds the no-protocol receive buffer
memory area.
2)
When data is transmitted from an external device before the
PC
CPU
reads the data received previously.
(3) AJ71C24
DTR control
(a) The size of the receive data storage area of
AJ71C24 OS
area is
279
bytes. It turns the DTR signal
ON
and
OFF
as follows:
0
less than
10
bytes storage area free
:
OFF
0
more than
41
bytes storage area free
:
ON
ON
ON
OFF
OFF
DTR
signal
I
ready AJ71 C24
memory
AJ71 C24 memory
(OS
wen) (OS area)
3-28
_.
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