Receive Signalling Circuits
Theory of Operation 5C.3-17
7.0 Receive Signalling Circuits
Refer to Figure 3.4 for reference for the following sections.
Figure 3.4 Receive Signalling Path.
7.1 Sub-audible Data (PL/DPL) and High Speed Data Decoder
The ASFIC (U0201) is used to filter and limit all received data. The data enters the ASFIC at U0201-
J7. Inside U0201 the data is filtered according to data type (HS or LS), then it is limited to a 0-5V
digital level. The MDC and trunking high speed data appear at U0201-G4, where it connects to the
µP U0101-11
The low speed limited data output (PL, DPL, and trunking LS) appears at U0201-A4, where it
connects to the µP U0101-10. While receiving low speed data, the µP may output a sampling
waveform, depending on the sampling technique, to U0201-C3 between 1 and 2 kHz.
The low speed data is read by the µP at twice the frequency of the sampling waveform; a latch
configuration in the ASFIC stores one bit every clock cycle. The external capacitors C0226, C0225,
and C0223 set the low frequency pole for a zero crossings detector in the limiters for PL and HS
data. The hysteresis of these limiters is programmed based on the type of received data. Note that
during HS data the µP may generate a sampling waveform seen at U0201-G1.
7.2 Alert Tone Circuits
When the software determines that it needs to give the operator an audible feedback (for a good key
press, or for a bad key press), or radio status (trunked system busy, phone call, circuit failures), it
sends an alert tone to the speaker.
It does so by sending SPI BUS data to U0201 which sets up the audio path to the speaker for alert
tones. The alert tone itself can be generated in one of two ways: internally by the ASFIC, or
externally using the µP and the ASFIC.
DET AUDIO
DISCRIMINATOR AUDIO
FROM RF SECTION
(IF IC)
G4
A4
GEPD 5431
C5
J3
G1
C3
J7
11
10
6 5
LOW SPEED
CLOCK
PL
IN
RX LIM
CAP
PL
LIM
RX
LIM
OUT
LOW SPEED
LIM CAP
HIGH SPEED
CLOCK
DATA FILTER
AND DEEMPHASIS
LIMITER
FILTER
LIMITER
ASFIC
U0201
MICRO
CONTROLLER
U0101
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