Transmitter Power Amplifier (PA) 5-25W
6.3-20 Theory of Operation
In transmit mode, this K9V1 voltage is high and biases Q8520 and, along with the RF signal from
Q8510, allows a collector current to be drawn. The collector current of Q8520 drawn from A+ flows
via L8542, L8541, directional coupler, D8551, L8551, D8631, L8631, R8616, R8617 and L8611 and
switches the PIN diodes D8551 and D8631 to the low impedance state.
D8551 leads the RF signal from the directional coupler to the harmonic filter. The low impedance of
D8631 is transformed to a high impedance at the input of the harmonic filter by the resonant circuit
formed by L8551, C8633 and the input capacitance of the harmonic filter.
In receive mode the low K9V1 and no RF signal present from Q8510 turn off the collector current of
Q8520. With no current drawn by Q8520 and resistor R8615 pulling the voltage at PIN diode D8631
to A+ both PIN diodes are switched to the high impedance state. The antenna signal, coming
through the harmonic filter, is channelled to the receiver via L8551, C8634 and line PA RX.
A high impedance resonant circuit formed by D8551 in off state and L8554, C8559 prevents an
influence of the receive signal by the PA stages. The high impedance of D8631 in off state doesn´t
influence the receiver signal.
9.5 Harmonic Filter
The transmitter signal from the antenna switch is channelled through the harmonic filter to the
antenna connector J8501.The harmonic filter is formed by inductors L8552, L8553, and capacitors
C8551 through C8554. This network forms a low-pass filter to attenuate harmonic energy of the
transmitter to specifications level. R8550 is used for electro-static protection.
9.6 Power Control
The power control loop regulates transmitter power with an automatic level control (ALC) loop and
provides protection features against excessive control voltage and high operating temperatures.
MOS FET device bias, power and control voltage limit are adjusted under microprocessor control
using a Digital to Analog (D/A) converter (U0731). The microprocessor writes the data into the D/A
converter via serial interface (SRL) composed of the lines SPI CLCK SRC (clock), SPI DATA SRC
(data) and DAC CE (chip enable). The D/A adjustable control voltage limit increases transmitter rise
time and reduces adjacent channel splatter as it is adjusted closer to the actual operating control
voltage.
The microprocessor controls K9V1 ENABLE (U0101-6) to switch on the first and the second PA
stage via transistors Q0741, Q0742 and signal K9V1. The antenna switch is turned on by the
collector current of the second PA stage. In TX mode the front-end control D/A (U0731-11) is used
for BIAS VOLTAGE 2 (via R0736) and K9V1 ENABLE pulls signal FE CNTL VLTG to ground via
Q0743. PA DISABLE, also microprocessor controlled (U0101-54), sets BIAS VLTG (U0731-4) and
VLTG LIMIT SET (U0731-13) via D0731 and BIAS VLTG 2 via D0733 in receive mode to low to
switch off the biases of the MOS FET devices Q8530, Q8531 and to switch off the power control
voltage (PWR CNTL).
Through an Analog to Digital (A/D) input (VLTG LIMIT) the microprocessor can read the PA control
voltage (PWR CNTL) during the tuning process.
The ALC loop regulates power by adjusting the PA control line PWR CNTL to keep the forward
power voltage PWR DETECT at a constant level.
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