Frequency Synthesis
4-30 Theory of Operation
The output signal of the phase detector is a pulsed DC signal which is routed to the charge pump.
The charge pump outputs a current at pin 29 (I OUT of U3701). The loop Þlter (which consists of
R3715 - R3717, C3723 - C3725, C3727) transforms this current into a voltage that is applied to the
varactor diodes D3732, D3733 (TX), D3751, D3752 (RX) and alters the output frequency of the TX
VCO (Q3741) and RX VCO (Q3751). The current can be set to a value Þxed in the FRAC-N IC or to
a value determined by the current ßowing into CPBIAS 1 (U3701-27). The current is set by the value
of R3723 and R3724. The selection of the two different bias sources is done by software
programming.
To reduce synthesizer lock time when new frequency data has been loaded into the synthesizer the
magnitude of the loop current is increased by enabling the IADAPT line (U3701-31) for a certain
software programmable time (Adapt Mode). The adapt mode timer is started by a low to high
transient of the FRACN CE line. When the synthesizer is within the lock range the current is
determined only by the resistors connected to CPBIAS 1 or the internal current source.
A settled synthesizer loop is indicated by a high level of signal LOCK DET (U3701-2). This signal is
routed to µP U0101-17 for further processing.
In order to modulate the PLL the two spot modulation method is utilized. Via pin 8 (MODIN) on
U3701 the audio signal is applied to both the A/D converter (low freq path) as well as the balance
attenuator (high freq path). The A/D converter converts the low frequency analog modulating signal
into a digital code that is applied to the loop divider, thereby causing the carrier to deviate. The
balance attenuator is used to adjust the VCOÕs deviation sensitivity to high frequency modulating
signals. The output of the balance attenuator is present at the MODOUT port (U3701-28) and
connected to the VCO modulation diode D3731.
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