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BIOS Setup
Advanced Chipset Features
Configure DRAM Timing by SPD
Selects whether DRAM timing is controlled by the SPD (Serial Presence Detect)
EEPROM on the DRAM module. Setting to [Auto] enables DRAM timings and the fol-
lowing related items to be determined by BIOS based on the configurations on the
SPD. Selecting [Manual] allows users to configure the DRAM timings and the follow-
ing related items manually. Setting options: [Manual], [Auto].
DRAM CAS# Latency
The field controls the CAS latency, which determines the timing delay before SDRAM
starts a read command after receiving it. Setting options: [By SPD], [2.5T], [2T]. [2T]
increases system performance while 2.5T provides more stable system performance.
Setting to By SPD enables DRAM CAS# Latency automatically to be determined by
BIOS based on the configurations on the SPD (Serial Presence Detect) EEPROM on
the DRAM module.
DRAM RAS# to CAS# Delay
This field allows you to set the number of cycles for a timing delay between the CAS
and RAS strobe signals, used when DRAM is written to, read from or refreshed.
Fast speed offers faster performance while slow speed offers more stable
performance. Setting options: [6 DRAM Clocks], [5 DRAM Clocks], [4 DRAM Clocks].
MSI Reminds You...
Change these settings only if you are familiar with the chipset.
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