MS-7640
Chapter 3
tRC
The row cycle tme determnes the mnmum number of clock cycles a memory row
takes to complete a full cycle, from row actvaton up to the prechargng of the actve
row.
tWR
Mnmum tme nterval between end of wrte data burst and the start of a precharge
command. Allows sense amplers to restore data to cells.
tRRD
Speces the actve-to-actve delay of derent banks.
tWTR
Mnmum tme nterval between the end of wrte data burst and the start of a column-
read command. It allows I/O gatng to overdrve sense amplers before read
command starts.
tRFC
Ths settng determnes the tme RFC takes to read from and wrte to a memory
cell.
Advanced Channel 1/ 2 Tmng Conguraton
Press <Enter> to enter the sub-menu. And you can set the advanced memory tmng
for each channel.
tRWTT02/ tWRRD2/ tWRWR2/ tRDRD2
These tems s used to set the memory tmngs for memory channel 1/ 2.
DCT Unganged Mode
Ths feature s used to Integrate two 64-bt DCTs nto a 128-bt nterface.
Bank Interleavng
Bank Interleavng s an mportant parameter for mprovng overclockng capablty of
memory. It allows system to access multple banks smultaneously.
HT Lnk Speed
Ths tem allows you to set the Hyper-Transport Lnk speed. Settng to [Auto], the system
wll detect the HT lnk speed automatcally.
Adjusted HT Lnk Frequency
It shows the adjusted HT Lnk frequency. Read-only.
CPU Core Control
Ths tem allows you to select the number of actve processor cores.
Unlock CPU Core
Ths tem s used to unlock the CPU core. Please refer to the procedures below for CPU
core unlocked n BIOS setup.
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