MSI H55M-E33 series - Memory Timing Settings; DRAM Timing Modes and Configuration; Advanced DRAM Timing Parameters

En-32
MS-7636 Manboard ▍
DIMM1~4 Memory SPD Informaton
Press <Enter> to enter the sub-menu. The sub-menu dsplays the nformatons of
nstalled memory.
Current DRAM Channel1~4 Tmng
It shows the nstalled DRAM Tmng. Read-only.
DRAM Tmng Mode
Select whether DRAM tmng s controlled by the SPD (Seral Presence Detect)
EEPROM on the DRAM module. Settng to [Auto] enables DRAM tmngs and the
followng “Advance DRAM Con󰘰guraton” sub-menu to be determned by BIOS based
on the con󰘰guratons on the SPD. Selectng [Manual] allows users to con󰘰gure the
DRAM tmngs and the followng related “Advance DRAM Con󰘰guraton” sub-menu
manually.
Advance DRAM Con󰘰guraton
Press <Enter> to enter the sub-menu.
CH1/ CH2 1T/2T Memory Tmng
Ths tem controls the SDRAM command rate. Select [1N] makes SDRAM sgnal
controller to run at 1N (N=clock cycles) rate. Selectng [2N] makes SDRAM sgnal
controller run at 2N rate.
CH1/ CH2 CAS Latency (CL)
Ths controls the CAS latency, whch determnes the tmng delay (n clock cycles)
before SDRAM starts a read command after recevng t.
CH1/ CH2 tRCD
When DRAM s refreshed, both rows and columns are addressed separately. Ths
setup tem allows you to determne the tmng of the transton from RAS (row address
strobe) to CAS (column address strobe). The less the clock cycles, the faster the
DRAM performance.
CH1/ CH2 tRP
Ths settng controls the number of cycles for Row Address Strobe (RAS) to be
allowed to precharge. If nsu󰘲cent tme s allowed for the RAS to accumulate ts
charge before DRAM refresh, refresh may be ncomplete and DRAM may fal to
retan data. Ths tem apples only when synchronous DRAM s nstalled n the
system.
CH1/ CH2 tRAS
Ths settng determnes the tme RAS takes to read from and wrte to memory cell.
CH1/ CH2 tRFC
Ths settng determnes the tme RFC takes to read from and wrte to a memory
cell.
CH1/ CH2 tWR
Mnmum tme nterval between end of wrte data burst and the start of a precharge
command. Allows sense ampl󰘰ers to restore data to cells.
CH1/ CH2 tWTR
Mnmum tme nterval between the end of wrte data burst and the start of a column-
read command. It allows I/O gatng to overdrve sense ampl󰘰ers before read
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