MSI X79A-GD65 8D - OC Menu - CPU and DRAM Settings; Adjusted CPU Frequency and EIST; Turbo Boost and Direct OC Buttons; DRAM Frequency and X.M.P

En-38
MS-7760 Manboard
Adjusted CPU Frequency
It shows the adjusted CPU frequency. Read-only.
EIST
Enhanced Intel SpeedStep technology allows you to set the performance level of the
mcroprocessor whether the computer s runnng on battery or AC power. Ths 󰘰eld only
appears wth nstalled CPUs that support ths technology.
Intel Turbo Boost 2.0
Enables or dsables Intel Turbo Boost 2.0 whch automatcally boosts CPU performance
above rated spec󰘰catons (when applcatons requests the hghest performance state
of the processor).
Drect OC Button
Ths tem allows you to enable/dsable the Drect OC buttons.
DRAM Frequency
Ths tem allows you to adjust the DRAM frequency. Please note the overclockng
behavor s not guaranteed.
Extreme Memory Pro󰘰le (X.M.P)
Ths tem s used to enable/dsable the Intel Extreme Memory Pro󰘰le (XMP). For further
nformaton please refer to Intel’s o󰘲cal webste.
Adjusted DRAM Frequency
It shows the adjusted DRAM frequency. Read-only.
DRAM Tmng Mode
Select whether DRAM tmng s controlled by the SPD (Seral Presence Detect)
EEPROM on the DRAM module. Settng to [Auto] enables DRAM tmngs and the
followng “Advanced DRAM Con󰘰guraton” sub-menu to be determned by BIOS based
on the con󰘰guratons on the SPD. Selectng [Lnk] or [Unlnk] allows users to con󰘰gure
the DRAM tmngs for each channel and the followng related “Advanced DRAM
Con󰘰guraton” sub-menu manually.
Advanced DRAM Con󰘰guraton
Press <Enter> to enter the sub-menu.
Command Rate
Ths settng controls the DRAM command rate.
tCL
Controls CAS latency whch determnes the tmng delay (n clock cycles) of startng
a read command after recevng data.
tRCD
Determnes the tmng of the transton from RAS (row address strobe) to CAS
(column address strobe). The less clock cycles, the faster the DRAM performance.
tRP
Controls number of cycles for RAS (row address strobe) to be allowed to pre-charge.
If nsu󰘲cent tme s allowed for RAS to accumulate before DRAM refresh, the DRAM
may fal to retan data. Ths tem apples only when synchronous DRAM s nstalled
n the system.
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