Nintendo Game Boy Advance - Programming Manual

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AGB-06-0001-002-B13

Released: May 27, 2005

Programming Manual

Version 1.35

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1999-2005 NINTENDO

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Table of Contents3
Revision History13
Introduction21
Using this Manual22
Figure 1 - Bit Operation Attribute Symbols22
The Game Boy Advance System23
System Overview23
System Configuration25
CPU Block Diagram25
Figure 1 - Game Boy Advance CPU Block Diagram25
Complete Block Diagram26
Figure 2 - Complete Game Boy Advance System Block Diagram26
Memory Configuration and Access Widths27
Little-Endian27
Table 1 - Game Boy Advance Memory Configuration and Access Widths27
Figure 3 - Game Boy Advance CPU Memory Addresses (Little-Endian)27
Game Boy Advance Memory29
Overall Memory Map29
Figure 4 - Game Boy Advance System Memory Map29
Memory Configuration30
Game Boy Advance Internal Memory30
Game Pak Memory31
Game Pak Memory Wait Control31
Figure 5 - the WAITCNT Register32
Table 2 - Game Pak Memory Wait Control Values33
Access Timing34
Table 3 - Wait Control Values and Wait Cycles34
Figure 6 - Sequential Access Timing Chart34
Figure 7 - Random Access Timing Chart34
Game Pak Bus35
Table 4 - Game Pak Bus Terminals35
Lcd37
Table 5 - Game Boy Advance Display Screen Features37
Figure 8 - Display Screen Horizontal and Vertical Blanking Intervals37
LCD Status38
Counter38
General LCD Status38
Figure 9 - the VCOUNT Register38
Figure 10 - the DISPSTAT Register38
Image System41
Figure 11 - the DISPCNT Register41
Modes43
Details of BG Modes43
Table 6 - Background Mode Details (Character Format BG Screen)43
Table 7 - Background Mode Details (Bitmap Format BG Screen)44
VRAM Memory Map45
Figure 12 - Background Mode Memory Maps45
Rendering Functions47
Character Mode BG (BG Modes 0-2)47
Control47
Table 8 - Background Mode Registers47
Figure 13 - Background Screen Control Registers48
Figure 14 - Text Background and Rotation/Scaling Background Screen Control Registers48
Table 9 - Screen Size Settings49
Figure 15 - Text Background Screen Sizes49
Figure 16 - Rotation/Scaling Background Screen Sizes50
Mosaic Size51
Figure 17 - the MOSAIC Register51
Figure 18 - Mosaic Schematic51
VRAM Address Mapping of BG Data52
Figure 19 - VRAM Base Blocks for Background Data53
Character Data Format54
Figure 20 - 16-Color X 16-Palette Character Data Format54
Screen Data Format55
Figure 21 - 256-Color X 1-Palette Character Data Format55
Figure 22 - Text Background Screen Format56
Figure 23 - Rotation/Scaling Background Screen Format56
Screen Data Address Mapping for the LCD Screen57
Figure 24 - Virtual Screen Size of 256 X 256 Pixels (Text Background)57
Figure 25 - Virtual Screen Size of 512 X 256 Pixels (Text Background)58
Figure 26 - Virtual Screen Size of 256 X 512 Pixels (Text Background)58
Figure 27 - Virtual Screen Size of 512 X 512 Pixels (Text Background)59
Figure 28 - Virtual Screen Size of 128 X 128 Pixels (Rotation/Scaling Background)59
Figure 29 - Virtual Screen Size of 256 X 256 Pixels (Rotation/Scaling Background)60
Figure 30 - Virtual Screen Size of 512 X 512 Pixels (Rotation/Scaling Background)60
Figure 31 - Virtual Screen Size of 1024 X 1024 Pixels (Rotation/Scaling Background)61
Rotation and Scaling Features62
Figure 32 - Referencing Rotated Background Data62
Figure 33 - Registers for Setting the Starting Point of BG Data63
Figure 34 - Registers for Setting the Direction Parameters of BG Data63
Scrolling64
Figure 35 - Offset Settings Registers64
Bitmap Mode Bgs (BG Modes 3-5)65
Control65
Rotation/Scaling65
Figure 36 - Offset Illustration65
Figure 37 - the BG2CNT Register65
Pixel Data66
Pixel Data Address Mapping for the LCD Screen66
Figure 38 - 32,768-Color Simultaneous Display Format66
Figure 39 - 256-Color Display Format66
Table 11 - BG Mode 4 (Frame 0)67
Table 12 - BG Mode 4 (Frame 1)67
Table 13 - BG Mode 5 (Frame 0)68
Table 14 - BG Mode 5 (Frame 1)68
OBJ (Object)69
OBJ Function Overview69
Table 15 - OBJ Function Features69
Character Data Mapping70
Table 16 - Rendering Cycles and the Corresponding Number of Displayable Objects70
Figure 40 - VRAM 2-Dimensional Mapping for OBJ Characters71
Figure 41 - VRAM 1-Dimensional Mapping for OBJ Characters71
Oam72
Figure 42 - Writing Rotation/Scaling Parameters to OAM73
Figure 43 - OBJ Attribute 074
Figure 44 - Cropping When Displaying a Scaled or Rotated Object75
Figure 45 - Cropping When Displaying a Magnified Character76
Figure 46 - OBJ Attribute 177
Figure 47 - Object Sizes77
Figure 48 - OBJ Attribute 278
OBJ Rotation/Scaling Feature79
Figure 49 - OBJ Character Data Referenced with Rotation79
Display Priority of OBJ and BG80
Priority Among Bgs80
Priority Among Objs80
Figure 50 - Object Rotation/Scaling Parameters80
Priority Among Bgs and Objs81
Figure 51 - Background and Object Priority81
Figure 52 - Color Palette RAM Memory Map84
Figure 53 - Referencing Palette RAM for OBJ and BG Modes84
Figure 54 - Color Data Format85
Figure 55 - Window Position Setting Registers87
Figure 56 - Window Display Priority Example87
Figure 57 - the WININ Register88
Figure 58 - the WINOUT Register88
Figure 59 - the BLDCNT Register89
Table 17 - Specifications for the BLDCNT Register90
Table 18 - EVA, EVB, and EVY Values91
Figure 60 - the BLDALPHA and BLDY Registers91
Figure 61 - Α Blending between OBJ and BG92
Figure 62 - Game Boy Advance Sound System Block Diagram93
Figure 63 - Sound FIFO Input Registers94
Table 19 - Sound 1 Frequency Change Bits95
Figure 64 - the SOUND1CNT_L Register95
Figure 65 - the SOUND1CNT_H Register96
Figure 66 - Waveform Amplitude Peak Proportions97
Figure 67 - the SOUND1CNT_X Register97
Figure 68 - the SOUND2CNT_L Register98
Figure 69 - the SOUND2CNT_H Register99
Figure 70 - the SOUND3CNT_L Register100
Table 20 - Sound 3 Output Level Selections101
Figure 71 - the SOUND3CNT_H Register101
Figure 72 - the SOUND3CNT_X Register101
Figure 73 - Waveform RAM Registers103
Figure 74 - the SOUND4CNT_L Register104
Figure 75 - the SOUND4CNT_H Register105
Table 21 - Sound 4 Prescalar Input Clock Selection106
Figure 76 - the SOUNDCNT_L Register106
Figure 77 - the SOUNDCNT_X Register107
Figure 78 - the SOUNDCNT_H Register108
Figure 79 - the SOUNDBIAS Register109
Table 22 - PWM Modulation Amplitude Resolution and Sampling Cycle Frequency110
Figure 80 - PWM Conversion Image110
Figure 81 - Timer Setting Registers111
Figure 82 - Timer Control Registers111
Table 23 - Timer Control Prescalar Selection112
Figure 83 - DMA 0 Source Address Registers114
Figure 84 - DMA 0 Destination Address Registers114
Figure 85 - the DMA0CNT_L Register114
Figure 86 - the DMA0CNT_H Register115
Table 24 - DMA Transfer Timing Selections (DMA 0)116
Figure 87 - DMA 1 and 2 Source Address Registers117
Figure 88 - DMA 1 and 2 Destination Address Registers117
Figure 89 - DMA 1 and 2 Word Count Registers118
Figure 90 - DMA 1 and 2 Control Registers119
Table 25 - DMA Transfer Timing Selections (DMA 1 and 2)120
Figure 91 - DMA 3 Source Address Registers121
Figure 92 - DMA 3 Destination Address Registers121
Figure 93 - the DMA3CNT_L Register122
Figure 94 - the DMA3CNT_H Register122
Table 26 - DMA Transfer Timing Selections (DMA 3)123
Table 27 - Communication Functions129
Figure 95 - Connecting During Normal Serial Communication130
Figure 96 - SIO Timing Chart (8-Bit Communication)131
Figure 97 - the SIODATA8 Register131
Figure 98 - 32-Bit Normal Serial Communication Data Registers132
Figure 99 - the SIOCNT Register (32-Bits)132
Figure 100 - Normal Serial Communication Flow (Example)134
Figure 101 - Multi-Player Communication Connection Status135
Figure 102 - Multi-Player Communication Timing Chart136
Figure 103 - Multi Player Game Boy Advance Game Link Cable Connecting Diagram137
Figure 104 - the SIOMLT_SEND Register137
Figure 105 - Multi-Player Data Registers137
Figure 106 - Multi-Player Data Transitions138
Figure 107 - the SIOCNT Register (16-Bit)139
Table 28 - Normal Serial Communication Baud Rates140
Figure 108 - Multi-Player Communication Flow (Example)141
Figure 109 - UART Communication142
Figure 110 - the SIODATA8 Register142
Figure 111 - Serial Communication Without FIFO142
Figure 112 - Serial Communication with FIFO143
Figure 113 - Example: Writing Data Registers143
Figure 114 - the SIOCNT Register (UART)144
Table 29 - UART Communication Error Conditions145
Table 30 - UART Communication Baud Rates146
Figure 115 - the RCNT Register (General-Purpose Communication)147
Figure 116 - the RCNT Register (JOY Bus Communication)148
Figure 117 - the JOYCNT Register148
Figure 118 - JOY Bus Receive Data Registers149
Figure 119 - JOY Bus Send Data Registers149
Figure 120 - the JOYSTAT Register149
Table 31 - the JOY Bus Reset Command150
Table 32 - the Type/Status Data Request Command150
Table 33 - the JOY Bus Data Write Command151
Table 34 - the JOY Bus Data Read Command151
Figure 121 - Game Boy Advance Game Link Cable Connection Types153
Figure 122 - the KEYINPUT Register155
Figure 123 - the KEYCNT Register155
Figure 124 - the IME Register157
Figure 125 - the IE Register157
Figure 126 - the if Register158
Figure 127 - System-Allocated Area in Work RAM159
Table 35 - System Status While in Stop Mode163
Table 36 - Terminology for Entering Sleep Mode from the Menu Screen164
Table 37 - Terminology for Entering Sleep Mode Using a Buttons Shortcut165
Table 38 - Terminology for Automatically Entering Sleep Mode165
Table 39 - System Status While in Halt Mode166
Figure 128 - Game Boy Advance ROM Registration Data171
Figure 129 - Device Type Bits172

Nintendo Game Boy Advance - Programming Manual

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