408A Manual
The “B” command can be used to access to all of
the AD9854 internal registers. While not a real-time
simulation of a high speed, each
“B”
command
functions as a parallel input by putting a data byte
“dd” at an address “aa”, and then pulses the
WRB- and IOUD lines on the AD9854.
All modes and set up conditions for the Analog
Devices AD9854 can be accessed by using the
“B”
command. Please consult the AD9854 specifications
for detailed operation.
Note that the 408A firmware modes are not identical
to the AD9854 data sheet modes.
4.10 The use of an external clock scales the fre-
quency output of the 408A. Using the 10MHz exam-
ple of the serial mode description (where F
setting
is
the total binary value sent to the 408A):
µ
µ
4.11 Note that values of F
setting
greater than 2
47
-1
violate the Nyquist Theorem Limit for the 408A as it
is a sampled data system.
4.12 The on-board Voltage Controlled Temperature
Compensated Crystal Oscillator (VCTCXO) can be
adjusted approximately
±
5ppm from nominal by
applying a 0 to 5Volt signal on P3. Your voltage con-
trol must be capable of sourcing and sinking 0.5mA.
The nominal unloaded voltage at calibration is
2.37Volts. This feature is useful for applications
which require Phase Locking to external sources,
using customer supplied circuitry.
4.13 For systems requiring locking to an external
reference, the Model LPO30A can be used to gener-
ate an external reference for the 408A. The LPO30
can generate the required 28,147,497.6710656 MHz
external clock with a maximum error of 0.4µHz, or a
fractional frequency error of 1.4x10
-14
, when locked
to an external source.
4.14 For applications which require amplitude
NOVATECH INSTRUMENTS
matching between the I and Q channels, the recom-
mended method is to use the “Vx N” command to
adjust the I or Q channel to match the other.
5.1 Please refer to the simplified System Block Dia-
gram in Figure 3 for the following discussion.
5.2 At every cycle of the 408A master clock, the 48-
bit DDS integrated circuit increments the phase of
an internal register by a value determined by the fre-
quency setting loaded into the on-chip registers.
This digital phase value is converted to both sine
and cosine amplitude levels and delivered to on-chip
12-bit digital-to-analog converters. The analog sig-
nals from these converters are filtered by two 7th-
order elliptical low pass filters, amplified and sent to
the Cos(I) and Sine(Q) OUT BNC receptacles.
5.3 The filtered cosine signal is also sent to an on-
chip comparator converting the cosine level to a
3.3V ACMOS/TTL level signal which is then sent to
the ACMOS/TTL OUT BNC receptacle. See speci-
fications for output level details.
5.4 The frequency generated by the DDS IC is
determined by the 48-bit frequency word loaded into
the frequency register on the 408A. The output fre-
quency is given by:
Where: F
clock
= 28,147,497.6710656 Hz (int.)
F
setting
= Binary value in DDS IC.
(F
setting
ranges from 0 to 2
47
-1)
Kp = PLL Multiplier (4 to 20, or 1)
This reduces to:
µ
for the internal (default) clock and the default PLL
Multiplier (Kp=10) settings.
5.5 Since the DDS IC is a sampled data system, the
output frequency is limited to a maximum of 1/2 the
master clock frequency (F
setting
<= 2
47
-1). While it
is possible to generate an output near 50% of the
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